Overview of PSL/Sugar support by EDA vendors PSL/Sugar Consortium Meeting DATE 04 Adriana Maggiore Usage of PSL/Sugar in Functional Verification  Simulation    Formal Verification    Assumptions about input constraints Assertions to prove about the.

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Transcript Overview of PSL/Sugar support by EDA vendors PSL/Sugar Consortium Meeting DATE 04 Adriana Maggiore Usage of PSL/Sugar in Functional Verification  Simulation    Formal Verification    Assumptions about input constraints Assertions to prove about the.

Overview of
PSL/Sugar support by
EDA vendors
PSL/Sugar Consortium
Meeting
DATE 04
Adriana Maggiore
Usage of PSL/Sugar in Functional
Verification

Simulation



Formal Verification



Assumptions about input constraints
Assertions to prove about the design
Hybrid Flows


Constraint inputs for test generation
Monitors for observability, coverage and error localisation
Combined simulation and formal verification
Others

Assertion development, protocol libraries, synthesis, training
PSL/Sugar support by EDA
vendors
Simulation
Formal
Hybrid + Others
@HDL
0-in
Cadence
Esterel
FTL
IBM
Mentor Graphics
Novas
Safelogic
Summit
SynaptiCAD
TransEDA
Verisity
@HDL
0-in
IBM
Real Intent
Safelogic
TransEDA
Veritable
@HDL
0-in
Doulos
IBM
Safelogic
TransEDA
PSL Sugar Support
 Model Checking for assertions written in PSL
• Full BDD based and bounded model checking
• Hierarchical model checking
• Incremental and Distributed model checking
• Complex constraint specification and state reduction
Automatic extraction of complex properties into PSL :
• FSM Deadlock, Multi-cycle path, False path, FIFO’s
• Reset logic and clock synchronization
 Simulation support for automatic PSL assertions into
industry standard simulators (NC, VCS, MTI, Finsim)
 Integrated debugging environment for PSL through
@Designer for formal and simulation results
@HDL – Feb 2004 – www.atHDL.com
Assertion StudioTM
Technology
Waveform
DB / VCD
Interpreter
[ Patent-pending ]
User PSL
Written
SVA
STEP 1
STEP 2
Verification
@HDL
PSL Assertion
Studio
Unified
Simulation & Formal
ABV
Formal
Engines
Sim
Engines
• Pass / Fail
• @HDL PSL Engine for Sim
• @Verifier, DP, ZX for Formal
Assessor
• Statistical Analysis
• Regression Analysis
behavior of assertions
without simulating
• Modifying and
Testing faulty assertions
STEP 3
Timing
Diagrams
Visualizer
STEP 5
• Verifying correct
Explorer
STEP 4
• Detailed assertion execution analysis
• Tracing the causes of failing/passing assertions
• Use Interpreter for modified assertions
@HDL – Feb 2004 – www.atHDL.com
0-In® Assertion-Based
Verification Suite
0-In CheckerWare® library
PSL
Assertions
» Verification IP with structural coverage
» Pre-verified, encapsulated assertions macros focused on RTL
functionality, e.g. arbiter, fifo, etc.
» Built on standard design and assertion languages
0-In CheckerWare monitors
» Verification IP for standard protocols, e.g. PCI Express, SPI-4,
Hypertransport, AMBA, DDR SDRAM, etc.
» Simple to use assertions capturing complex behaviors
Archer Verification™ System
Verify PSL
Assertions
» Dynamic formal verification to automatically, exhaustively
exercise corner-cases
» Static formal verification (model checking) to find deep bugs
0-In Design Automation Copyright 2004
6
Cadence PSL/Sugar Support
Cadence Language Position
• Cadence is committed to ensure unified standards for advanced design
and verification
• Cadence provides current and continuing support for the VHDL, Verilog
(incl. SystemVerilog extensions), PSL/OVL, SystemC, Verilog-AMS,
and VHDL-AMS standards
PSL/Sugar in the Cadence Incisive Verification Platform
• Native compilation and execution of PSL/Sugar assertions
• Optimizes PSL/Sugar assertions into Incisive single kernel engine
• PSL/Sugar assertions are treated as verification objects
• Interactive simulation & debugging: breakpoints, interrogation, probing
CADENCE CONFIDENTIAL
Incisive Debug Environment
Double-clicking
on Assertion name
brings up the
assertion source
Assertion failures
shows up as events
on a probe.
Assertion activity
is recorded as a
transaction
Goto-cause on
failure event
brings up the
assertion source
CADENCE CONFIDENTIAL
Independent Language &
Methodology Training
Doulos have announced training
and reference support for
PSL/Sugar
• Assertion-based Verification
using PSL (1-day course)
• Expert VHDL & Verilog courses
upgraded to include PSL coverage
• Tool specific PSL training
• PSL Golden Reference Guide



Esterel Technologies Support of PSL / Sugar
Esterel Technologies is
committed to support
interoperability between Esterel
Studio and the assertion
standard PSL/Sugar
Esterel Technologies is currently
implementing support of a PSL +
Esterel simulation flow for its
customers
Simulation Flow
Esterel IP design + PSL/EDL asserts
Esterel
IP design
PSL / EDL
assertions
Esterel
Compiler
FoCs
VHDL / Verilog
Esterel technologies is planning
to support static verification of
PSL properties with Esterel
Studio designs
 Definition of PSL subset and PSL flavor
supported within Esterel Studio is
planned for 2005, as a result of current
customer interactions. Esterel Technologies Confidential
VHDL / Verilog
HDL Simulator
Property Specification Language (PSL)
Version 1.01 Support in Release 9
Auriga Highly Parallel Verification
Environment uses PSL verification
directives to validate designer intent
Merlin Behavioral Synthesis
Environment uses PSL to
implement designer intent
Ongoing, funded work coordinated by FTL Systems provides for
analog/mixed signal and asynchronous extensions to PSL
Auriga and Merlin are trademarks of FTL Systems Inc. & FTL Systems UK Ltd. For further information see
http://www.ftlsystems.com or write [email protected] For further information on analog/mixed signal
and asynchronous extensions, please contact John Willis at FTL Systems, [email protected]
PSL/Sugar Support in IBM’s Verification Tools
Formal
P
Assertions
Assertions
Simulation
IBM RuleBase Parallel Edition:
Static Property Checking via Parallel FV
• PSL support :
– Fully supports the simple subset, which can be checked "onthe-fly“
– Supports advanced constructs, e.g. sequence operators, abort,
named sequences, named properties, forall
• Powerful formal model checking platform
– Optimized for PSL/Sugar
– Capable of handling very large design models
– Automatic state-space reduction leaves only parts relevant to
verified properties
– Optimized for 3 modes of operation
• exhaustive search, partial search and adaptive search
The RuleBase Parallel Edition Platform:
Two Tiers of Parallel FV
• Coarse-Grain Parallel FV
RTL
+
PSL
formal
engine
slave
slave
slave
Engine
Dispatcher
– Central engine dispatch
point
– Distribution of multiple
verification tasks
• Fine-Grain Parallel FV
formal
engine
slave
slave
slave
– Decomposition of a large
verification tasks into smaller,
tractable subtasks
FoCs (Formal Checkers)
• Function
- Runtime (“dynamic") checking of PSL assertions during
simulation
• Features
- Generates Verilog/VHDL/C++ monitors from PSL properties
– functional checking + coverage tracking
- Optimized for RTL simulation
- Synthesizable RTL produced - applicable for emulation
- Independent of simulator and methodology
- User-friendly self-explanatory GUI
Mentor Graphics PSL Support

Initial Tool Support: ModelSim 5.8
—

Built-in assertion engine
—
—

Announced on Oct 27, 2003
PSL available now
Supports both embedded and file-based
assertions
Integrated into ModelSim debug
environment
—
—
New Assertion Browser
Cross referenced to all windows to speed
up debugging

Wave, Source, Dataflow
VHDL
PSL
Assertions
System
Verilog
Verilog 2001
AMS
C/C++
SystemC
Mathworks
ModelSim
5.8
Coverage
HW/SW
Debug
Novas PSL and SVA Assertion-Driven Debug


Load and view assertion
source and results

View assertion/design
association

Waveform shows
assertion pass/fail
Trace assertion “drivers”
and “loads” across design


Verdi engine quickly finds
root cause
Post-process captured
signal data (FSDB) to
check assertions


Cause-and-effect details
Automatically trace
assertion failures


PSL Source Code
- can be traced
Verdi Automatic Tracing
Check new assertions
without re-running
simulation
Other supported assertion
languages

OVA
Novas Software, Inc. • • Way Beyond Waveforms
Pass/Fail Waveform
Verix from Real Intent:
A Complete Formal Assertion Verification System
•
•
•
•
•
Automatic Formal Assertions
User-specified Assertions in PSL
Formal Asynchronous Clock Domain
Checking
Automatic, Scalable Hierarchical Formal
Analysis
Verilog, VHDL, and Mixed Language
Support
Safelogic property verification
methodology
1. Run Safelogic Monitor for design/property sanity check
2. Run Safelogic Verifier to select strategy per design block or property
3A. Run Safelogic Monitor on any
problem to boost simulation results
www.safelogic.se
3B. Run Safelogic Verifier on
blocks/properties that are
’appropriate’ or of certain interest
Visual Elite™ PSL Flow
 Visual Elite
provides a
seamless assertionbased design flow
 The PSL source
resides as a side
object in the
browser and is
seamlessly
processed through
IBM’s FoCs
 Assertions
generated during
simulation
Design
PSL/Sugar
FoCs
Assertions
Simulate
SynaptiCAD TestBencher Pro
Generates test benches for VHDL, Verilog, TestBuilder, & SystemC
TestBencher
generates entire
verification system
including Sugar
assertions.
With TestBencher, users
describe protocols using
graphical timing diagrams.
Verification
systems need to
model different
protocols.
Generated Sugar
assertions used to verify
protocol compliance.
SynaptiCAD Transaction Tracker
Analyze transaction data during and after simulation
Transaction Tracker
locates transactions using
Sugar expressions.
Users enter temporal
expressions using Transaction
Tracker Sugar Wizard.
Transactions are displayed
as extra signals in the
waveform window.
Transaction Tracker can
identify transactions during
and after simulation.
TransEDA support for PSL

imPROVE-HDL: Formal Property Checker
• Includes Hardware Protocol Kits (HPKs) for Automatic
and Exhaustive Protocol Formal Verification
• Use PSL to add design-specific properties

VN-Property: Simulation-based Property Checker
• Links property coverage to code-coverage with VN-Cover
• Includes HPKs for Automatic Protocol Verification
• Use PSL to add design-specific properties
PSL as Part of a Total Verification Solution

Specman Elite® : Testbench Automation


Automates verification process with directed-random test
generation, data/assertion checking, functional coverage analysis
PSL assertions embedded in HDL and/or testbenches


Used as runtime checkers
Provides additional coverage metrics
–


Total coverage: Functional, Code, and Assertion Coverage
Links to formal verification
PSL assertions embedded in e verification language


Enables code sharing between simulation and formal
Enables reuse of HDL assertion in more powerful testbenches
Coverage and Assertion Interface
External coverage
& assertion sources
Specman Elite
SureCov™
Sugar/PSL
Checking
CAI
Coverage
OVL
…
Verity-Check Expert
 Formally checks user specified temporal properties
Automatic state space reduction without user guidance
 More than order of magnitude faster than model checkers
 Multi-million gate capacity allows full chip verification

 Properties can be specified using Accellera PSL/Sugar

Supports Verilog flavor of PSL
 Property violations result in generation of test sequences

Counter-examples displayed as waveforms or testbench generated
 Easy to use, robust tool

Used in production flows since 2001