DPS sa FPGA Direktna implementacija FIR filtara Direktni FIR filtar b[L–1] b[L–2] p[L–1] p[L–2] SOP: PROCESS (a,p) BEGIN FOR I IN 0 TO L-2 LOOP -- Compute the transposed a(I) END.
Download ReportTranscript DPS sa FPGA Direktna implementacija FIR filtara Direktni FIR filtar b[L–1] b[L–2] p[L–1] p[L–2] SOP: PROCESS (a,p) BEGIN FOR I IN 0 TO L-2 LOOP -- Compute the transposed a(I) END.
DPS sa FPGA Direktna implementacija FIR filtara Direktni FIR filtar b[L–1] b[L–2] p[L–1] p[L–2] SOP: PROCESS (a,p) BEGIN FOR I IN 0 TO L-2 LOOP -- Compute the transposed a(I) <= (p(I)(W2-1) & p(I)) + a(I+1); -- filter adds END LOOP; a(L-1) <= p(L-1)(W2-1) & p(L-1); -- First TAP has y <= a(0); END PROCESS SOP; b[L–3] b[0] p[L–3] p[0] Load: PROCESS BEGIN WAIT UNTIL clk = '1'; IF (Load_x = '0') THEN c(L-1) <= c_in; -- ucitavanje koeficijenta FOR I IN L-2 DOWNTO 0 LOOP -- pomeranje koeficijenata c(I) <= c(I+1); END LOOP; ELSE MulGen: FOR I IN 0 TO L-1 GENERATE b(L-1) <= x_in; -- Muls: ucitavanje ulaza lpm_mult -- p(i) = c(L-1-i) * b(i); FOR I IN L-2 DOWNTO GENERIC 0 LOOP --MAP pomeranje ulaza ( LPM_WIDTHA => W1, LPM_WIDTHB => W1, b(I) <= b(I+1); LPM_PIPELINE => Mpipe, END LOOP; LPM_REPRESENTATION => "SIGNED", END IF; LPM_WIDTHP => W2, END PROCESS Load; LPM_WIDTHS => W2) a[L–2] a[L–3] PORT MAP ( clock => clk, dataa => b(I), datab => c(L-1-I), result => p(I)); END GENERATE; a[0] Zauzetost komponente • LE: 163 • MULT: 4 • 216.73MHz PROCESS MulGen: FOR I IN 0Load: TO L-1 GENERATE BEGIN Muls: lpm_mult -- Multiply p(i) = c(i) * x; UNTIL clk => = '1'; GENERIC MAP (WAIT LPM_WIDTHA W1, LPM_WIDTHB => W1, IF (Load_x = '0') THEN LPM_PIPELINE => Mpipe, f(L-1) <= f_in; --=>preuzimanje LPM_REPRESENTATION "SIGNED", koeficijenta FOR I IN L-2 DOWNTO 0 LOOP -- shiftovanje keoficijenata LPM_WIDTHP => W2, f(I) <==>f(I+1); LPM_WIDTHS W2) END LOOP; PORT MAP ( clock => clk, ELSE dataa => x, x <= x_in;=> p(I));-- sample datab => f(I), result END IF; END GENERATE; END PROCESSSOP: Load;PROCESS (clk) BEGIN IF clk'event and (clk = '1') THEN FOR I IN 0 TO L-2 LOOP a(I) <= (p(I)(W2-1) & p(I)) + a(I+1); END LOOP; a(L-1) <= p(L-1)(W2-1) & p(L-1); END IF; y <= a(0); END PROCESS SOP; Transponovani FIR filtar p[L–1] a[L–1] p[L–2] p[L–3] a[L–2] a[L–3] p[0] a[0] Zauzetost komponente • LE: 184 • MULT: 4 • 216.73MHz