Transcript Here> RAPID Memory Compiler Evaluation

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RAPID Memory Compiler Evaluation
by David Artz
Oracle Labs
November 2011
Overview of <Vendor A> SRAM/RF Compilers
• A competitive assessment against TSMC memory
compilers is not available at this time as we are still
waiting on legal access to said technology. <Insert Picture Here>
• Features:
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Speed and/or high density
Aspect ratio control for floor planning
Memory operation and retention at low frequency
Low active power and leakage-only standby power
Views/models
Extra Margin Adjustment (EMA)
Soft Error Repair (SER)
Redundancy
Over-the-cell power routing
Maximum static power dissipation corner
Power gating
Pipeline register
Advanced Test Feature (ATF)
2
Speed and/or High Density
40 nm SRAM Memory Compilers
Maximum Size
Memory Solution Architecture
Mux Options
(Kbits)
Single Port
Single Port
Dual Port
Speed
Density
Density
576
1152
320
8, 16, 32
8, 16, 32
4, 8, 16
40nm Register File Memory Compilers
Maximum
Memory Solution Architecture
Mux Options
Size (Kbits)
Single Port
Speed
32
2, 4, 8
Single Port
Density
144
2, 4, 8
Two Port
Density
72
1, 2, 4
Single Port SRAM, High Speed, 0.374um2 Bit Cell, 64 Rows/Bank
Muxing
Parameters
8
16
32
min
256
512
1024
Words
max
4096
8192
16384
step
32
64
128
min
4
4
4
Number of
max
144
72
36
Bits/Word
step
1
1
1
Single Port SRAM, High Density, 0.229um2 Bit Cell, 256 Rows/Bank
Muxing
Parameters
8
16
32
min
256
512
1024
Words
max
4096
8192
16384
step
32
64
128
min
4
4
4
Number of
max
144
72
36
Bits/Word
step
1
1
1
Dual Port SRAM, High Density, 0.589um2 Bit Cell, 256 Rows/Bank
Muxing
Parameters
4
8
16
min
64
128
256
Words
max
2048
4096
8192
step
32
64
128
min
4
4
4
Number of
max
144
72
36
Bits/Word
step
1
1
1
3
Aspect Ratio Control for Floor Planning
8
16
32
4
Memory Operation and Retention at Low Frequency
Before going into retention mode, the
memory needs to be in standby mode
by setting CEN =1.
The CLK pin must be held low before a
high or low transition of RET1N, in
accordance with the timing arcs
specified in the Liberty model. Once this
is accomplished, set RET1N=0. The
power is still supplied to the memory
core and the periphery.
The word lines are clamped low.
VDDPE can now be shut down and
VDDCE may be varied within the limits
required in Power gating compiler
manual.
5
Views/Models
Standard Views
Verilog model
SER Verilog
VCLEF footprint
GDSII layout file
Synopsys (Liberty) for each corner
LVS netlist
Synopsys (Liberty) TetraMAX
VoltageStorm
Hercules
CeltIC enablement
Datasheets
Output Files
<instance_name>.v
<instance_name>_rtl.v a
<instance_name>.vclef
<instance_name>_ant.lef
<instance_name>_ant.clf
<instance_name>.gds2
<instance_name>_<ccs/nldm/ecsm>_corner_syn.lib b,c,d
<instance_name>.cdl
<instance_name>.tv
N/A
N/Ae
N/Af
ASCII datatable <instance_name>_corner.dat
Postscript <instance_name>.ps
a)
The word-write mask option should be set to off when SER is selected as either 1db1bc or 2bd1bc.
b)
You can create timing models using any of the process-voltage-temperature (PVT) corners for which the memory compiler was
characterized. The compiler may support more than four characterization corners, however, you can create timing models for
only four corners at a time. The characterization corner name (slow, fast, fast@-40C, fast@125C, typical) is inserted into the
output filename (for example, sram_sp_<corner>_syn.lib).
c)
Synopsys models are generated with maximum alternate current (AC) values for each supported corner. Depending on chip
design, overall chip level worst case power conditions can occur under the fast corner (PVT conditions) or under the “maximum
static power” corner condition. The worst case static power occurs under the maximum temperature, fast process, and
maximum VDD. The static power corner models both AC and static power under this condition. You may need to perform chip
level power analysis under both the fast and static power corners to determine the maximum overall power dissipation, AC plus
static, for your design.
d)
Includes CCS timing , noise, and power data.
e)
Hercules LVS/DRC is supported in the case of available decks.
f)
CeltIC views or files are not provided by the compiler.
6
Extra Margin Adjustment (EMA)
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•
Extra margin adjustment pins provide the option of
adding delays into internal timing pulses. There are three
sets of EMA pins: EMA[2:0], EMAS, EMAW[1:0].
Use of the EMA[2:0] pins provides extra time for memory
read and write operations by slowing down the memory
access. There are three input pins, named EMA[2],
EMA[1], EMA[0], for each instance. The access time and
cycle times are progressively increased as the pins are
driven from 000 to 111 respectively. The EMA[2:0] pins
are always visible. Margin sequentially increases as
EMA sequentially increments from 000 through 111.
Setting 000 is the fastest setting and 111 is the slowest
setting. Minimum EMA setting for given operating range
is documented in the model .lib file.
When enabled, the EMAS pin extends the pulse width of
the sense-amp enable signal. The default setting is low
but when driven high the pulse is extended. The setting
on this pin does not affect the access time, but it will
affect cycle time in the read cycle.
When enabled, the EMAW[1:0] pins add delay for write
cycles. They do not affect the access and cycle time
during read operation (GWEN=1). The write access and
cycle time is the sum of EMA[2:0] and EMAW[1:0].
7
Over The Cell Power Routing
You must route chip-level ground (VSS)
and VDD to the memory instance and
drop vias down to the m4 straps.
memory periphery
memory core
In order to maintain power density for
each strap, use multiple top-level grid
connections with a maximum spacing of
15um and a minimum width to provide
coverage for a via array count of three.
The top supply metal in SRAM compilers
is m4. To meet instance IR drop
requirements, m5 straps at least 0.21um
wide for VDDPE, VSSE, and VDDCE
must be located over the instance,
perpendicular to the instance m4 supply
strap direction, and within 10um of the
instance edge.
memory periphery
VDD for core (VDDCE)
VSS
chip level m5 power
routing
In addition, a pattern of VDDPE, VSSE,
and VDDCE m5 straps, each at least
0.21um wide, must be repeated across
the instance at 15um intervals. Each
intersection of instance supply m4 and
overlapping, perpendicular supply strap
m5 should be maximally contacted.
VDD for periphery (VDDPE)
m4
VSS
m5
Via 4-5
over the cell m4 routing grid
8
Power Gating
VDDPE
VDDCE
Mode
B1
VDDCE
*VDDCE
VDDPE
<= *VDDCE
PGEN
0
RET1N
X
RET2N
X
RETP
X
Operation
Normal
Outputs
Q (normal outputs)
Description
This is normal operational mode.
Clamped to VDDPE
Here the row lines are clamped low and all
outputs are clamped to VDDPE. The active
power gates in the core are switched on. You
directly control the core retention voltage
through VDDCE. The periphery power gates
are off. This shuts down the periphery
power. You vary VDDCE, but VDDCE must be
greater than or equal to VDDPE at all times.
Clamped to VDDPE
Here the row lines are clamped low and all
outputs are clamped to VDDPE. The active
power gates in the core are switched off and
the HVT retention devices are on. The
retention voltage of the core is controlled by
the diode-connected HVT pMOS devices. The
periphery power gates are off. This shuts
down the periphery power. Both VDDCE and
VDDPE should remain powered up.
Clamped to VDDPE
Here the row lines are clamped low and all
outputs are clamped to VDDPE. The active
power gates in the core are switched off and
the SVT retention devices are on. The
retention voltage of the core is controlled by
the diode-connected SVT pMOS devices. The
periphery power gates are off which shuts
down the periphery power. Both VDDCE and
VDDPE should remain powered up.
Clamped to VDDPE
Here both the core array and the periphery
are powered down. This shuts down the
memory and all state information is lost. All
outputs are clamped to VDDPE. Both VDDCE
and VDDPE should remain powered up.
Memory Macro
Core
B2
*VDDCE
<= *VDDCE
1
0
X
X
Retention 1
Periphery
VSSE
VSSE
B3
Net Name
Overview
VDDCE
External core
voltage domain
vddc,
Internal core
vddc<#:#> voltage domain
VDDPE
External
periphery
voltage domain
vddp
Internal
periphery
voltage domain
VSSE
External ground
domain
vss
Internal ground
domain
Details
This external core voltage supply is the supply seen
by the off-chip. It connects to all core domain NWells. It also connects to all core domain pMOS
power gate sources.
This internal core voltage domain connects to all core
domain pMOS sources unless the source is never
connected to a virtual power rail.
This external periphery voltage supply is the supply
seen by the off-chip. It connects to all periphery NWells. It also connects to the periphery domain pMOS
power gate sources for the row
line drivers.
This internal periphery voltage supply connects to the
periphery pMOS sources unless the gate is never
connected to a virtual power rail. This means in only
the row driver NOR gates will use vddp.
This external ground supply is the supply seen by the
off-chip. It connects to all P-Wells. It also connects to
all nMOS sources in the core domain as well as nMOS
sources in the periphery domain which are never
connected to a virtual ground rail.
This internal ground domain will connect to all
periphery domain nMOS sources unless the source is
never connected to a virtual ground rail.
B4
B5
*VDDCE
*VDDCE
*VDDCE
<= *VDDCE
<= *VDDCE
<= *VDDCE
1
1
1
1
1
1
0
0
1
0
1
X
Retention 2a
Retention 2b
Power Down
9
Power Gating (cont).
Mode
B1
B2
B3
B4
B5
100.00
Peak
Core
3.558
Built w/Power Gating Option
Off
On
Peri
Total
Core
Peri
51.914
55.473
3.665
52.972
CEN=1, 50% Activity
0.203
1.943
2.146
0.202
1.943
CEN=1, 0% Activity
Retention
Retention 2A
Retention 2B
Transition
Power-Down
0.203
0.203
#N/A
#N/A
#N/A
#N/A
0.091
0.006
#N/A
#N/A
#N/A
#N/A
0.294
0.208
#N/A
#N/A
#N/A
#N/A
0.204
0.201
0.063
0.074
0.201
0.031
0.095
0.038
0.038
0.038
0.038
0.038
Condition
100.00
64Kbit SRAM w/No Power Gating
2.146
0.299
0.239
0.101
0.112
0.239
0.069
64Kbit SRAM w/Power Gating
10.00
Current (mA)
Current (mA)
10.00
Total
56.637
1.00
1.00
Periphery
0.10
Core
B1
B2
B3
0.01
B4
Periphery
0.10
B5
Core
B1
B2
B3
B4
B5
0.01
Modes
Modes
10