Dsd lecture 2
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Transcript Dsd lecture 2
Digital System Design
EEE344
Lecture 2
Introduction to Verilog HDL
Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock
1
Steps of solving digital design problem
Problem Statement
Define the problem in simple words
Think and write about what is required
HDL Description/ Design Entry
Divide the tasks
Write Verilog code for each task
Logic Simulation
Subject your code to simulator
Functional Errors are checked
Logic Synthesis and implementation
Timing Verification
Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock
2
HDLs (hardware descriptive languages)
Common HDLs are :
Verilog HDL
VHDL
Some other HDLs
AHDL, System C etc
History of Verilog® HDL
Beginning: 1983
“Gateway Design Automation” company
IEEE standardised
Simulation environment
Comprising various levels of abstraction
Switch (transistors), gate, register-transfer, and higher levels
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History of Verilog® HDL (cont’d)
Three factors to success of Verilog
Programming Language Interface (PLI) i.e. that allows behavioral code to invoke C
functions and C code to invoke Verilog system tasks.
Close attention to the needs of ASIC foundries
“Gateway Design Automation” partnership with Motorola, National, and UTMC in 1987-89
Verilog-based synthesis technology
“Gateway Design Automation” licensed Verilog to Synopsys
Synopsys introduced synthesis from Verilog in 1987
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History of Verilog® HDL (cont’d)
VHDL
VHSIC (Very High Speed Integrated Circuit) Hardware Description Language
Developed under contract from DARPA
IEEE standard
Public domain
Other EDA (electronic design automation) vendors adapted VHDL
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History of Verilog® HDL (cont’d)
Today
Market divided between Verilog & VHDL
VHDL mostly in Europe
Verilog dominant in US
VHDL
More general language
Not all constructs are synthesizable
Verilog:
Not as general as VHDL
Most constructs are synthesizable
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Verilog HDL
Verilog built-in primitives:
N-input
N-output, 3-state
and
buf
or
not
nand
bufif0
nor
bufif1
xor
notif0
xnor
notif1
How to write Verilog code?
Starting statement/keyword
module
Ending keyword
endmodule
Complete Verilog code looks like
module <name of the design>( ports list separated by comma,s);
<ports declaration>
<body code of your design>
end module
Example 1
module half_adder (sum, c_out, a,b);
input a,b;
output c_out, sum;
xor (sum,a,b);
and (c_out,a,b);
endmodule
Example 2
When we connect two primitives we use a keyword wire
module simple1(y_out,x1,x2,x3,x4,x5);
input x1,x2,x3,x4,x5;
output y_out;
wire y1,y2;
and (y1,x1,x2);
nand (y2,x3,x4,x5);
nor (y_out,y1,y2);
endmodule
Some language rules
Verilog is case-sensitive language
The name of a variable may not begin with a digit or $ , and may not be
longer than 1024 characters.
Comments may be embedded in two ways 1) // 2) /* */
Top-Down Design and Nested modules
Complex design is partitioned into sub-blocks
Each sub-block is designed and checked its functionality
A separate module is designed that combines all the sub-blocks
Example 1
Full Adder
w1 xor cin
Cin
Half Adder 2
a
b
w1=a xor b
w3
OR
gate
Half Adder1
w2=a.b
sum
cout
Example 2
a[15:0]
b[15:0]
cin
16bit ripple carry adder
16 bit ripple carry adder
cout
sum[15:0]
Example 16bit RCA
a[15:12] b[15:12]
b[11:8]
a[11:8]
a[7:4]
a[3:0]
b[7:4]
b[3:0]
cin
ut
c3
RCA4
sum[15:12]
c1
c2
RCA3
sum[11:8]
RCA2
sum[7:4]
RCA1
sum[3:0]
Example 4bit RCA
a[3]
b[3]
b[2]
a[2]
a[1]
b[0]
a[0]
b[1]
cin
ut
c3
fa4
sum[3]
c1
c2
fa3
sum[2]
fa2
fa1
sum[1]
sum[0]
Full adder
Full Adder
w1 xor cin
Cin
Half Adder 2
a
b
w1=a xor b
w3
OR
gate
Half Adder1
w2=a.b
sum
cout
Example 2bit comparator
A
A1 A0
B
A_lt_B
A_gt_B
A_eq_B
B1B0
00
00
1
00
01
1
00
10
1
00
11
1
01
00
01
01
01
10
1
01
11
1
10
00
1
10
01
1
10
10
10
11
11
00
1
11
01
1
11
10
1
11
11
1
1
1
1
1
A_lt_B
B1B0
00
01
11
10
A1A0
00
A1’B1
1
01
1
1
1
1
11
10
1
A1’A0’B0
A_lt_B= A1’A0’B0 + A0’B1B0 + A1’B1
A0’B1B0
A_gt_B
B1B0
00
01
11
10
A1A0
00
A0B1’B0’
01
1
11
1
1
10
1
1
1
A1B1’
A_gt_B = A1B1’ + A1A0B0’ + A0B1’B0’
A_eq_B = A1A0B1B0+ A1’A0’B1’B0’ + A1’A0B1’B0+ A1A0’B1B0’
A1A0B0’
4bit comparator
Four bit comparator can be developed from two 2bit comparators as follow:
Four bit comparator has two four bit inputs(A has A3A2A1A0, B has B3B2B1B0 bit
positions), and three scalar outputs similar to 2bit comparator.
The four bit comparator will consist of two 2bit comparators i.e. first comparator
will have A3A2B3B2 inputs and A_gt_B, A_lt_B, A_eq_B outputs, second
comparator has inputs A1A0B1B0 and A_gt_B, A_lt_B, A_eq_B outputs.
For A_gt_B of 4bit comp: if either A_gt_B of first 2bit comp is one or if A_eq_B of
first 2bit comp is one and A_gt_B of second 2bit comp is one, then A_gt_B of 4bit
comp is 1.
A_gt_B = (A_gt_B of 1st comp ) or ((A_eq_B of 1st comp) and (A_gt_B of 2nd comp))
..
Similarly for A_lt_B:
A_lt_B = (A_lt_B of 1st comp ) or ((A_eq_B of 1st comp) and (A_lt_B of 2nd comp))
For A_eq_B:
A_eq_B= ((A_eq_B of 1st comp) and (A_eq_B of 2nd comp))
a3
4bit comp
Grt
b3
Les
a_gt_b
a2
b2
Eq
and
or
a_Lt_b
a1
b1
or
Grt
Les
a0
b0
and
a_eq_b
and
Eq
Four value logic
0
1
X
Z
Test Methodology
Stimulus generator
Unit under test
Response Monitor
Test bench or stimulus writing steps
Module test();
Wire inputs;
Reg outputs;
UUT a1(ports);
Initial begin
Variables values
$monitor("a=%b b=%b c=%b d=%b w=%b y=%b", variable waveforms);
end
endmodule
End