Transcript cp-progress
Cluster Processor Chip • Requirements 70 trigger towers 160 Mbit/s Din[107:0] (BC Multiplexed) – Capture and synchronise – BC-De mux and error checking Reset-DLL – e/g, t/h Algorithm System Clock-1 • Cluster Hits • RoIs – Readout of RoIs Read out via VME System Clock-2 En-Cal Reset-Global Error Serial to Parallel Converter & Synchronisation to LHC Clock BCID De-Mux & Error Detect Threshold Registers DLL x4 Clock Alignment Logic Reset/Load -Countes Wr Address 18 (L) 18 (R) Dual Port RAM (40 X 128 deep) Rd Address Load-ShiftReg Hits[31:0] e/g, t/h Trigger Logic & ROI Logic Zero Hits Saturation • 108 at 160 Mbit/s Data Monitor 'Scan Path' (Second Configuration) En-Scan Error – Process 4 x 2 x 2 TT Window – Receive BC multiplexed data Offset En-Read-out (L) (R) FIFO-FF Data-VME[15:0] 20 bit ROI ROS Addr-VME [9:0] 20 bit ROI FIFO (40 x 64 deep) VME CS* Rd/Wr* FIFO-EF RoI-Data_L 0 Shift register @ 40MHz RoI-Data_R Rd/Wr-Strobe 0 DAQ/Level-2 data via ROD JTAG Port 4 RAL Instrumentation System Design Group Shift register @ 40MHz RoI Read-out Logic Viraj Perera 2-March-01 Cluster Processor Chip • Requirements – Set-up and diagnostic Logic (second configuration) 108 trigger towers (BC Multiplexed) System Clock En-Cal Serial to Parallel Converter & Synchronisation to LHC Clock 432 bits Data Monitor 'Scan Path' 160 Mbit/s Din[107:0] DLL x4 Clock Alignment Logic Data-VME[15:0] 1- 16 registers (16 time slices) Scan-Enable JTAG Port 4 RAL Instrumentation Scan path readout System Design Group Viraj Perera 2-March-01 Cluster Processor Chip • CP Chip Status All logic blocks designed and integrated Serial to Parallel conversion and Synchronisation BCID De-multiplexing logic Algorithm Readout logic Set-up and diagnostic logic implemented as a second configuration – More simulations to be done • Test vectors supplied by Steve Hillier RAL Instrumentation System Design Group Viraj Perera 2-March-01 Cluster Processor Chip • Device – Fits in XCV1000E-6 • Latency – Seven, 40 MHz clock ticks (-6 device) RAL Instrumentation System Design Group Viraj Perera 2-March-01