Transcript Pseudo Arithmetic Structure For Test Data

Fitting ATE Channels with Scan
Chains: a Comparison between a Test
Data Compression Technique and
Serial Loading of Scan Chains
J. DALMASSO, M.L. FLOTTES , B. ROUZEYRE
LIRMM
CNRS / University of Montpellier II
FRANCE
1
Outline
• Introduction and motivation
• Serialization vs compression ?
• Compression technique
• Results
• Conclusion
2
Needs for Test Data Compression
 Integration density 
• Number of transistors 
• Number of faults to test 
• Test data volume 
• Test time 
=> Multiple scan chains
 ATE limits:
• Memory depth
• # ATE channels
3
Issue
N scan chains,
M ATE channels,
N>M
ATE
M
N
How to fit M with N ?
CUT
4
1) Serialization of test data
1 Test slice
1 Pattern
1 test pattern = L test slices
1 test slice = divided into N/M slices of M bits in ATE
 Short test sequences (No X's)
5
2) Horizontal (de)compression
6
Test pattern compression
Netlist
dependent
Virtual scan chains (VTS'00)
Illinois scan architecture (DATE'02)
Ring generator+phase shifter (ITC'02)
Circular scan (DATE'04)
Test data mutation encoding (DATE'02)
Xor network (DAC'01)
Reconfigurable Switch (ITC'01)
Dictionnary based methods (TDAES'03 / & ITC'04)




Test data
dependent
Specific tool
dependent





Long test sequences (due to X's, low fill rate)
7
Issues
Given: M ATE channels, N scan chains, N > M
 Fitting M with N ?
– Serialization : short test sequences (No X's)
– Compression : long test sequences (X's)
 What is the best solution ?
8
Proposed horizontal compression method
 Features
Circuit netlist independent (suitable for IPs)
Test data independent (additional test patterns)
Specific tools independent
Low cost hardware decompressor
 Input: test data sequence
actually applied to CUT
No impact on fault coverage
Take advantage of X's in test sequence
9
Decompressor architecture
M
0
0
0
From ATE
0
Add
Cells
Output
Shift Register
N
To scan chains
10
Decompression principle
Let Si = aN-1………………..…...…….a0
Let Si+1 = bN-1…………………..………b0
1/ it exists Sci = cM-1……c0 / Si+1 = Si + Sci
c1
0
0
c0
0
0
aN-1…………………………………..…...…….a0
11
Decompression principle
Let Si = aN-1………………..…...…….a0
Let Si+1 = bN-1…………………..………b0
1/ it exists Sci = cM-1……c0 / Si+1 = Si + Sci
dist
c1
0
0
0
c0
0
bN-1…………………………………………..…b0
1 slice on N bits (Si+1) => 1 slice of M bits (Sci) in ATE
Remark : P(cj: aibi) = 1/ 2dist
=> uniform distribution of inputs over adders
12
Decompression principle
Let Si = aN-1………………..…...…….a0
Let Si+1 = bN-1…………………..………b0
2/ it does not exist Sci = cM-1……c0 => serial loading of Si+1
b2M+1
bM+1
b1
A slice on N bits (Si+1) => N/M slices of M bits in ATE
b2M
bM
b0
13
Compression
• Case 1 : it exists Sci on M bits => 1 slice of M bits
• Case 2 : it does not exist Sci => N/M slices of M bits
• Compression
– Maximize case 1 occurrences
– Presence of X's
• Columns ordering
• X's assignment
• Pattern ordering
14
Compression algorithm: columns ordering
P(cj: aibi) = 1/ 2dist
ATE Channels
ATE Channels
S1:
0
X
1
X
S1:
1
X
X
0
S2:
S3:
1
X
1
1
X
X
X
0
S2:
X
1
X
1
S3:
X
1
0
X
S4:
1
X
X
X
S4:
X
X
X
1
Scan Chains
Scan Chains
15
Compression algorithm: X's assignment
I=1
Si coded
on N bits
while i< #Slices
shift mode
Initialization of Si
If
i++
SCi
YES
SCi assignment
Si+1 = Si + SCi
i++
NO
add mode
SCi coded
on M bits
END
16
Initialization and assignment
ATE Channels
Init =>
S1:
S2:
S3:
S4:
S5:
1
X
X
X
X
X
X
0
1
X
X
1
X
X
0
0
X
X
X
1
X
X
X
0
X
1
0
1
0
0
X
X
X
0
1
X
0
X
X
X
0
X
X
X
X
1
0
1
0
0
0
0
0
0
1
SC1: 0 1 0
SC2: 0 1 0
SC3 : 1 1 0
SC4 : - - -
Scan chains
Init =>
S1:
S2:
S3:
S4:
S5:
1
1
1
1
X
0
0
0
1
X
1
1
1
0
0
0
0
0
1
1
0
1
1
0
X
0
0
0
0
X
0
0
0
0
X
17
Compression algorithm: X's assignment
I=1
Si coded
on N bits
while i< #Slices
shift mode
Initialization of Si
If
i++
SCi
YES
SCi assignment
Si+1 = Si + SCi
i++
NO
add mode
SCi coded
on M bits
END
18
Compressed Slice assignment
a
S1
S2
S3
S4
S5
1
X
X
X
X
0
X
0
1
X
b
1
1
X
X
0
0
X
X
X
1
0
X
X
0
X
c
1
0
1
0
0
0
X
X
0
1
0
0
X
X
X
0
X
X
X
X
?
a b c S1
010
011
S2
010
S3
110
S4
S5
S2
011
S3
111
S4
001
S5
19
Example
Init =>
S1:
S2:
S3:
S4:
S5:
1
X
X
X
X
X
X
0
1
X
S1:
S2:
S3:
S4:
S5:
X
1
X
X
0
1
1
1
1
1
0
X
X
X
1
X
X
X
0
X
1
0
1
0
0
X
X
X
0
1
X
0
X
X
X
0
X
X
X
X
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
0
0
0
0
0
1
SC1 :
SC2 :
SC3 :
SC4 :
0
0
1
1
0
011
011
111
001
0
1
0
1
0
20
Pattern ordering
V0
V1
V2
V3
V1
V2
V2
V4
V4
• Pattern order has an influence
on the number of compressed
slices
 Comparison of Pattern
Ordering Algorithm:
 Greedy algorithm
 Simulated Annealing
V4
S5378, N = 8, M = 2, 41337 slices
Uncompressed
Gain (%)
Slices
V2
Initial Order
Greedy Algorithm
Simulated Annealing
1497
1182
930
0
21,04
37,87
21
Decompression synchronization
Scan
1
0 enable
0
1
1
0
Control
1
0
0
Original test Sequence
S1
S2
S3
1 0
1 0
1 1
0
0
1
0
1
0
S4
0 1
1
0
S1 -> S2 : 0 1
1
0
X
0
1
0
1
X
S2 -> S3 : 1 1
S3 -> S4 : - -
1
0
Compressed test Sequence
1
0
X
1
X
0
1
X
0
0
X
1
1
X
0
1
X
0
1
X
1
0
X
1
X
0
X
0
X
0
1
X
FSM
CLK
Sc1
Sc2
Sc3
Sc4
Sc5
Sc6
1
0
0
1
0
1
0
0
1
1
1
0
22
Compression vs serialization
Serialization
With Compression
Test Time (loading) = Depth
TSC  NSC
 N  
TSNC  NSNC      1
M 
 N  
T  P1  L      1  L  P1
M 
 N  
T  NSC  NSNC      1  L  P2
M 
1slice
Data Volume
VSC  NSC  M
N
VSNC  VSNC     M
M

 N 
V  M   NSC  NSNC    
M

N
V  M  L     P1
M
23
Experiments: Compression vs Serialization
• Test data sequences
– Compression : X's needed
• type 1 : no compaction
– long test sequences (very low fill rate)
• type 2 : compaction during ATPG
– medium size test sequences
– Serialization : No X's,
• type 3 : all ATPG optimizations enabled (fault
dropping, random filling, compaction …)
– short test sequences (fully specified)
– ATPG
24
Experimental results
type1: compression - 1531 patterns
L
N
M
%X
#Slices
original
volume
(bits)
1
27
7
8
32
N
27
8
7
32
comp
comp #comp.
Time
volume
ratio % Slices (cycles)
(bits)
#Slices
Gain
Volume (bits)
Time (cycles)
Volume
Time %
%
34560
39067
-58,843 -49,46
34560
21787
-167,17 -126,4
54896
83,4
39400
58391
92334
72,08
39727
49335
4
168020
49,19
40669
44231
34560
13147
-386,17 -236,4
2
53624
84,36
9644
29423
35840
19207
-49,621 -53,19
63111
81,6
9685
23607
36960
13607
-70,755 -73,49
101864
70,3
10045
14943
35840
5767
-184,22 -159,1
180032
47,5
10182
13325
35840
3527
-402,32 -277,8
2
3
8
16
L
type3: serialization - 160 patterns
95,98
96,12
41337
10717
330696
342944
type2: compression - 217 patterns
original
comp
comp # comp. Time
% X #Slices volume volume
ratio
% Slices (cycles)
M
(bits)
(bits)
1
13181
63,37
4813
14471
82,57
5859
46872
2
17670
59,41
4867
10071
4
25472
44,63
5350
7121
2
16928
47,91
1056
9151
3
18177
47,15
1065
6737
83,19 1519
48608
8
21992
45,17
1109
3383
16
29904
33,14
1169
2443
4320
1120
type3: serialization - 160 patterns
#Slices
Volume (bits)
Time (cycles)
34560
34560
34560
35840
36960
35840
35840
39067
21787
13147
19207
13607
5767
3527
4320
1120
S5378 circuit (214 flip-flops)
Gain
Volume
Time %
%
61,87
48,88
26,3
52,77
50,82
38,64
16,57
62,96
53,78
45,84
52,36
50,49
41,34
30,74
25
Experimental results
compression
serial loading
Gain
original comp. comp
#comp. Time
Volume Time Volume Time
#Pat % X #Slices volume volume ratio
#Pat #Slices
Slices (cycles)
(bits) (cycles) %
%
L
(bits) (bits)
%
Circuit
FF
s5378
214
7 217 83,19 1519 48608
21992 54.76
1109
3383
160
1120
35840
5767
38,64 41,34
s9234
247
8 215 77,3
1720 55040
30176 45.17
1036
4679
186
1488
47616
7634
36,63 38,71
s13207 699
22 272
93
5984 191488 65296
65.9
5258
9182
250
5500
176000
27772
62,9
s15850 611
20 142
84
2840 90880
42520 53.21
2015
6302
126
2520
80640
12746
47,27 50,56
s35932 1763 56 26
50
1456 46592
28256 39.35
764
4306
25
1400
44800
7081
36,93 39,19
s38417 1664 52 440 93,83 22880 732160 244192 66.65 20332
33564 145
7540
241280
37897
-1,2
11,43
s38580 1464 46 189 85,49 8694 278208 119448 57.07
17245 142
6532
209024
32848
42,85
47,5
6615
66,94
N= 32 scan chains , M = 8 ATE channels
26
Comparison with Circular Scan [*]
[*] B. Arslan, A. Orailoglu, "CircularScan: a scan architecture for test
cost reduction", DATE'04, pp: 1290-1295.
Gain with our method
s13207
s15850
s35932
s38417
s38584
N
M
32
6
Volume
62,62
50,74
32,94
53,44
56,45
Time
69,82
44,24
22,36
47,58
51,20
Gain with [*]
Volume
55,0
29,8
4,0
25,9
32,0
Time
54,6
29,8
6,2
25,4
32,1
27
Post process for regular circuits (not for IPs):
Fault simulation => Pattern Dropping
Compression &
X’s Assignment
Test Sequence
with X’s
Fully specified
Test Sequence : T
P1: 1 XX 1 0 X 0 1
f1, f2
P1: 1 1 0 1 0 0 0 1
f1, f2
P2: XX 1 XX 1 0 X
f3
P2: 1 0 1 1 0 1 0 1
f3, f1, f2
Pattern rejection algorithm
P
Pattern
T
T*
With P* ≤ P
P*
Pattern
28
Pattern Dropping Algorithm
Without pattern dropping
#FF
N
L
M Volume Depth Time
s5378
214
214
8
32
27
7
#P
With pattern dropping
Volume Depth Time
214
Volume
Time
#P
14372 14372 15855
209
11272 11272 12455
159
21,57
21,44
23,92
2
4
17514
25368
8757 10031
6342 7277
209
209
13914
20112
6957
5028
7999
5741
163
167
20,55
20,72
20,26
21,11
22,01
20,10
2
21676 10838 11679
209
15560
7780
8391
160
28,22
28,15
23,44
21999
25096
31600
209
209
209
15429
18152
22896
5143
2269
1431
5712
2815
1915
159
163
159
29,86
27,67
27,54
29,79
28,02
29,15
23,92
22,01
23,92
3
8
16
N
L
s5378
214
#P
1
7333
3137
1975
8136
3911
2703
serial loading - 160 p.
#FF
Gain Pattern Dropping (%)
8
32
27
7
M Volume Depth Time
GAINS (%)
#P
VOLUME TIME
1
34560 34560 39067
160
67,38
68,12
2
4
34560 17280 21787
34560 8640 13147
160
160
59,74
41,81
63,29
56,33
2
35840 17920 19207
160
56,58
56,31
3
36960 12320 13607
160
58,25
58,02
35840
35840
160
160
49,35
36,12
51,19
45,70
8
16
4480
2240
5767
3527
29
Conclusion
• Simple horizontal compression technique
Circuit netlist independent (suitable for IPs)
Test data independent
Specific tool independent
• Effective alternative to serialization
Compacted test sequences vs fully specified
sequences
30
Pattern Dropping Algorithm
For i=1 to #Pi in T
Add Pi to T*
i++
Fault simulation of T*
i++
Number of detected faults: fdi
If fdi > fdi-1
Remove Pi from T*
NO
YES
End For
New test
sequence T*
31
Compression process summary
Column Ordering
Pattern Ordering
Compression
Pattern Dropping
standard circuits only
32
Perspectives
Other sequential decompressor structures
Co-optimization test architecture / compression
test time: tam sizing / wrapper sizing / decompressor
33
State Of The Art
 At the CUT inputs (when test vectors are applied)
 At the CUT outputs (when the test responses are checked)
34
State of The Art
Output Compression
• Time compaction (MISR based solutions)
• Risk of aliasing
• Diagnosis difficult
» Koenemann (IBM) ITC’01
• Spatial compaction (Xor trees based solutions)
• Presence of unknown values
» Mitra ITC’02
• Mixed methods
e.g. Convolutional compactors
» Rajski (MENTOR) ITC’04
35