Transcript Microcontroller : Cypress PSoC 5 LP

2014/10/27
Microcontroller :
Cypress PSoC 5 LP
EE-446 Embedded Architectures
Typical Microcontroller Purposes
• The purpose for microcontroller is
to interface multiple types of
hardware
 Digital Input/Outputs
 Switches
 Relays
 LEDs
Computer
uC
Thermal
 Digital Communications: I2C, SPI
Gyro
 Analog Input/Outputs
Acceleration
1
2014/10/27
Example of Hardware Interfacing
Regular Microcontroller Caveats
• What if you need more Analog Inputs?
• What if you need more Interrupts?
• Advanced projects: more PWMs needed?
 Use external circuitry
 Buy a larger microcontroller
2
2014/10/27
Cypress PSoC 5 LP
Why Cypress PSoC ?
 PSoC is a true programmable embedded SoC integrating
configurable analog and digital peripheral functions, memory
and a microcontroller on a single chip
3
2014/10/27
PSoC 3 / PSoC 5 Platform Architecture
CPU Subsystem
ARM Cortex-M3
• Industry’s leading embedded CPU company
• Broad support for middleware and applications
• Up to 80 MHz; 100 DMIPS
• Enhanced v7 ARM architecture:
• Thumb2 Instruction Set
• 16- and 32-bit Instructions (no mode switching)
• 32-bit ALU; Hardware multiply and divide
• Single cycle 3-stage pipeline; Harvard architecture
8051
• Broad base of existing code and support
• Up to 67 MHz; 33 MIPS
• Single cycle instruction execution
4
2014/10/27
CPU Subsystem
High Performance Memory
• Flash memory with ECC
• High ratio of SRAM to flash
• EEPROM
Powerful DMA Engine
• 24-Channel Direct Memory Access
• Access to all Digital and Analog Peripherals
• CPU and DMA simultaneous access to independent
SRAM blocks
On-Chip Debug and Trace
• Industry standard JTAG/SWD (Serial Wire Debug)
• On chip trace
• NO MORE ICE
CPU Subsystem
Clocking System
• Many Clock Sources
• Internal Main Oscillator
• External clock crystal input
• External clock oscillator inputs
• Clock doubler output
• Internal low speed oscillator
• External 32 kHZ crystal input
• Dedicated 48 MHz USB clock
• PLL output
• 16-bit Clock Dividers
• 8 Digital
• 4 Analog
• PSoC Creator Configuration Wizard
• PSoC Creator auto-derive clocking source/dividers
5
2014/10/27
CPU Subsystem
Dedicated Communication Peripherals
•
Full Speed USB device
• 8 bidirectional data end points + 1 control end point
• No external crystal required
• Drivers in PSoC Creator for HID class devices
•
Full CAN 2.0b
• 16 RX buffers and 8 TX buffers
•
I2C master or slave
• Data rate up to 400 kbps
• Additional I2C slaves may be implemented in UDB
array
High-Precision Analog
 Best of Both Worlds:
 High-precision, dedicated analog
 Flexible, programmable analog
 DSP-like digital filter capability
 Rich library of pre-built, characterized
components
6
2014/10/27
Analog Subsystem
Configurable Analog System
•
•
•
•
•
•
•
•
•
•
Flexible Routing: All GPIO are Analog
Input/Output
+/- 0.1% Internal Reference Voltage
Delta-Sigma ADC: Up to 20-bit resolution
• 16-bit at 48 ksps or 12-bit at 192 ksps
SAR ADC: 12-bit at 1 Msps
DACs: 8 – 10-bit resolution, current and
voltage mode
Low Power Comparators
Opamps (25 mA output buffers)
Programmable Analog Blocks
• Configurable PGA (up to x50), Mixer,
Trans-Impedance Amplifier, Sample and
Hold
Digital Filter Block: Implement HW IIR and
FIR filters
CapSense Touch Sensing enabled
Powerful, Flexible Digital Logic
 Powerful PLD-based digital system
 Each UDB ≈ small 8-bit processor
 Optimized 16-bit Timer/Counter/PWM
Blocks
 Rich library of pre-built, characterized
components
7
2014/10/27
Programmable Routing/Interconnect
Input / Output System
• Three types of I/O
• GPIO, SIO, USBIO
• Any GPIO to any peripheral routing
• Wakeup on analog, digital or I2C match
• Programmable slew rate reduces power and noise
• 8 different configurable drive modes
• Programmable input threshold capability for SIO
• Auto and custom/lock-able routing in PSoC Creator
Up to 4 separate I/O voltage domains
• Interface with multiple devices using
one PSoC 3 / PSoC 5 device
PSoC 3 / PSoC 5 Platform Architecture
8
2014/10/27
PSoC 5 –
System Resources
Section Objectives
 Objectives, you will be able to:
• Understand the system block diagram of PSoC 5 devices
• Understand and use the PSoC 5 System Resources, including:
Power system
Programming & debugging
Clocking
Memory & mapping
DMA
I/O
Interrupts
9
2014/10/27
System Block Diagram
Power System and Supplies (no boost)
 Standard Power Configuration
•
No boost pump
•
Vdda Vddd >= Vddio 0/1/2/3
•
Vdda = 1.8 – 5.5V
Vddd
Vddio2
0.1µF
0.1µF
0.1µF
1.3µF
I/O Supply
Vddio0
I/O Supply
Vddio0
0.1µF
Digital
Regulator
• Supply Rules & Usage
•
Vdda: Must be highest voltage in system. Supplies
analog high voltage domain and core regulator.
•
Vddd: Supplies digital system core regulators
•
Vddio 0/1/2/3: Independent I/O supplies. May be any
voltage in the range of 1.8V to Vdda
I2C
Regulator
NC
Vssb
Ind
Vboost
Vbat
Vssd
High
Voltage
Analog
Domain
Low
Voltage
Digital
Domain
Sleep
Regulator
Vssd
Vdda
Analog
Regulator
Vssa
Vdda
0.1µF
1.3µF 0.1µF
Vcca
Hibernate
Regulator
Low
Voltage
Analog
Domain
I/O Supply
I/O Supply
0.1µF
Vddio1
0.1µF
Vddd
0.1µF
0.1µF
Vddio3
10
2014/10/27
Programming & Debug Interfaces
 JTAG
• Legacy 4-wire Interface
• Supports all programming and debug features
 Serial Wire Debug (SWD)*
• Standard 2-wire interface for all CY tools and kits
• Supports all programming and debug features with same performance of
JTAG
• Default debug interface in PSoC Creator
 Serial Wire Viewer (SWV)
• Supports 32 mailboxes for application “printf ” type debug
• Uses only 1 pin
Clocking Sources
Internal Main Oscillator: 3-67 MHz. (±1% at 3 MHz; ±5% at 67 MHz)
PLL output: 12-67 MHz (can not use 32 kHz crystal)
External clock crystal input: 4-33 MHz
External clock oscillator inputs: 0-33 MHz
Clock doubler output: 12-48 MHz
Internal Low speed oscillator: 1 kHz, 33 kHz and 100 kHz
External 32 kHz crystal input for RTC
3- 67 MHz
IMO
4- 33 MHz
ECO
0- 33 MHz
Ext Osc
32 kHz
ECO
1, 33 , 100 kHz
ILO
PLL
11
2014/10/27
Clock Distribution
 Clock dividers
 16-bit dividers
3- 67 MHz
IMO
 8 clock source inputs
 8 digital clock dividers
4- 33 MHz
ECO
0- 33 MHz
Ext Osc
32 kHz
ECO
1, 33,100 kHz
ILO
PLL
7
 4 analog clock dividers
• Provide skew control to reduce digital
switching noise
 1 CPU divider
 UDBs can be used to create
additional digital clocks
7
Digital Clock Divider
16-bit
Digital Clock Divider
16-bit
Bus/ CPU Divider
16-bit
Digital Clock Divider
16-bit
Digital Clock Divider
16-bit
Digital Clock Divider
16-bit
Analog Clock Divider
Skew
16-bit
Digital Clock Divider
16-bit
Analog Clock Divider
Skew
16-bit
Digital Clock Divider
16-bit
Analog Clock Divider
Skew
16-bit
Digital Clock Divider
16-bit
Analog Clock Divider
Skew
16-bit
System Clock Setup
12
2014/10/27
Clock Management
 Clocks allocated to dividers in clock tree
 Clocks have software APIs to dynamically change frequency
 Note: Reuse existing clocks to preserve resources
ARM Cortex-M3 Memory Map
Single 4 GB address space
• Registers from 8051 map into 0.5 GB peripheral region’s bit band region for
efficient bit operations
13
2014/10/27
Flash
Flash Blocks:
• 256 Blocks in all devices – 64 KB flash has 256 byte block size
• Each block may be set to 1 of 4 protection levels of increasing security
Unprotected – Allows internal and external reads and writes
Factory Upgrade – Prevents external read
Field Upgrade – Prevents external read and write
Full Protection – Prevents external read and write as well as internal write
• Flash is erased and programmed in block units
Specs:
•
•
•
•
•
Code executes out of Flash
Flash-writes block CPU unless executing from cache (PSoC 5 only)
20 year minimum retention
10k minimum endurance
15 ms block erase + write time
EEPROM
2 KB of EEPROM are provided
Code can not execute out of EEPROM
EEPROM Specs:
• EEPROM writes do not block CPU execution
• 20 year minimum retention
• 100k minimum endurance
• 2 ms single byte erase + write time
• Supports single byte erase and writes
• May erase or write up to 16 consecutive bytes (1 row) at the same time.
14
2014/10/27
Nonvolatile Latches (NV latches)
NV Latches
• Single Flash bits used to hold critical configuration data
• Required at power up before normal Flash can be read
• Used the same as fuse bits except resettable
• Uniquely capable of asynchronously outputting the bit state immediately on POR release
NV Latch Specs:
• 10 minimum endurance (Like fuse bits, not programmed often)
• 20 year minimum retention
• Set as required by PSoC Creator (System tab of DWRM)
• NV Latches are used for:
Each IO Port’s initial reset state (High-Z, pull-up, pull-down)
Optional XRES pin (P1[2]) enable
Configuration Speed (fast, slow)
Debug Port Selection (4-wire JTAG, 5-wire JTAG, SWD, None)
Error Correcting Code (ECC) enable
Digital clock phase delay (2.5 – 12.5 ns)
Direct Memory Access (DMA)
24 hardware channels
8 priority levels with minimum bandwidth guarantees
128 Transaction Descriptors (TD) tell channel what to do
•
2kB of dedicated SRAM holds all TD data
Multiple channels or TDs may be chained or nested
Configurable burst size
DMA between peripherals on same spoke limited to 1-byte burst length
15
2014/10/27
GPIO - I/O Digital Features
 Independent supply rails
• Each quadrant of device has separate Vddio
supply
(100 mA max sink or source)
• GPIO Vddio must be <= Vdda
 Logic level max current
• 8 mA sink
• 4 mA source

 Pin max current
• ~25 mA sink
• ~25 mA source
GPIO - I/O Digital Features
 8 Drive Modes
16
2014/10/27
GPIO - Interrupts
 Each GPIO port has:
• Port Interrupt Control Unit (PICU)
• Dedicated interrupt vector
 Interrupt on:
• Rising edge
• Falling edge
• Any edge
 Status Register
• Latches which pin triggered interrupt
• Available for firmware read
• Read clear
GPIO - I/O Analog Features
• All pins inputs and outputs
• Supports two independent analog
connections at each pin
• Some pins have additional routing
features:
• Opamps
• High Current DAC mode
• CapSense Touch Sensing
• LCD char/segment drive
• Hardware controlled analog mux at pin
17
2014/10/27
SIO (Special I/O) Features
Same as GPIO with exceptions:
• 5.5V tolerant at all Vdda levels
 Hot Swap
Digital Input Path
Programmable Input Buffer Config
 Overvoltage tolerance
CMOS or LVTTL
• Configurable drive and sense voltage levels
Digital Input
 Basic DAC output
Pin Interrupt Type Register
 High Speed CMP input
Interrupt Controller
• Logic level max current
Buffer
Thresholds
Pin Status Register
Pin Interrupt Status Register
Interrupt
Logic
Buffer Disable
Digital Output Path
Slow Slew Enable
 4 mA source
Data Register
• Pin max current
 ~50 mA sink
 ~25 mA source
• No Analog
Driver
Vhigh
Programmable Output Buffer Configuration
 25 mA sink
Digital Output
0
1
Data Register Bypass
5K
Drive Mode 2
Drive Mode 1
Drive Mode 0
Drive
Logic
Slew
Cntl
PIN
5K
Bidirectional Control
Bidirectional Enable
• No LCD char/segment drive
• No CapSense touch sensing
Pin Management
 PSoC Creator, CyFitter can select pins automatically
• Best to let fitter have maximum flexibility to optimize entire design
• Lock pins when device pin out is finalized
 Manual override in DWR file
18
2014/10/27
Interrupts
Interrupt Controller
• 32 interrupt vectors
• Dynamically adjustable vector addresses
• 8 priority levels
• Each vector supports one of three sources
Fixed function, DMA, DSI (UDB) route
8051
• 32 interrupt vectors vs. standard 8051 is five
ARM Cortex-M3
• 32 interrupts + 15 exceptions
• Tail chaining
Interrupt Component
GUI Configuration
API
isr_1_Start() – Configures and enables the interrupt. Typically the only API
required to be called
Advanced APIs
isr_1_SetVector() – Dynamically change vector address
isr_1_SetPriority() – Dynamically change vector priority
isr_1_GetPriority() – Read current priority
isr_1_Enable() – Enable interrupt vector
isr_1_GetState() – Return current state of interrupt vector enable
isr_1_Disable() – Disable interrupt vector
isr_1_SetPending() – Force a pending interrupt
isr_1_ClearPending() – Clear a pending interrupt
19
2014/10/27
Lab 1:
My First PSoC 5 Digital Design
Lab Objectives
 Objectives:
• Blink an LED on the EagleSoC Development Board
• Experience the PSoC Creator Design Flow
20
2014/10/27
Step 1: Start PSoC Creator
Step 2: Create a New Project
21
2014/10/27
Step 3: Place/Configure Digital Pin
Step 3: Place/Configure Digital Pin
22
2014/10/27
Step 4: Configure PSoC I/O
Step 5: Add main.c Code
23
2014/10/27
Step 5: Add main.c Code
Step 6: Build Project
24
2014/10/27
Step 7: Program/Debug
Step 8: Debug
25
2014/10/27
PSoC 5 –
PSoC Creator Design Flow
Section Objectives
 Objectives, you will be able to:
• Follow the PSoC Creator Design Flow and develop projects
• Find and use the tools available within the software IDE
• Compile, build and program PSoC 5 applications
• Debug PSoC 5 applications
26
2014/10/27
PSoC Creator Design Flow
 Configure
• Start a new project
• Place components
• Configure components
• Connect components
 Develop
• Build hardware design and generate component APIs
• Write application code utilizing component APIs
• Compile, build and program
 Debug
• Perform in-circuit debug using PSoC Creator
 Reuse
• Capture working hardware/software designs as your own components for future use
Open PSoC Creator
27
2014/10/27
PSoC Creator Software
Create a new project
Select the platform
Name the design
Select the device*
Select the sheet template*
* Optional steps
28
2014/10/27
PSoC Creator Design Canvas
Component Catalog
Catalog Folders
Analog
ADC
Amplifier
DAC
CapSense
Communications
Digital
Functions
Logic
Registers
Utility
Display
Filters
Ports and Pins
Power Supervision
System
Thermal Management
Catalog Preview
Datasheet access
29
2014/10/27
Adding Components to a Design
Pins, Logic and Clock Components
30
2014/10/27
Component Configuration
Double-click to open component configuration dialogs
Component Data Sheets
 Contents:
• Features
• General description of component
• When to use component
• Input/Output connections
• Parameters and setup
• Application Programming Interface
• Sample firmware source code
• Functional description
• DC and AC electrical characteristics
31
2014/10/27
Design-Wide Resource Manager (.cydwr)
 Pins
• Map I/O to physical pins and ports
• Over-ride default selections
 Analog
 Clocks
 Interrupts
• Set priority and vector
 DMA
• Manage DMA channels
 System
• Debug, boot parameters, sleep mode API generation, etc.
 Directives
• Over-ride placement defaults
 Flash Security
 EEPROM
Interrupts
Priority may be changed
Defaults to 7 (lowest priority)
32
2014/10/27
DMA
Priority may be changed
Defaults to 2 (0 & 1 can consume 100% of bandwidth)
System
System settings
Debug settings
Voltage Configuration
33
2014/10/27
Clock Configurations
System Clocking Tree
34
2014/10/27
Pin Editor
Connecting Components
35
2014/10/27
Build Hardware Design
Build Process
Generate a Configuration
•
•
•
•
•
•
•
•
•
•
Design Elaboration
Netlisting
Verilog
Logic Synthesis
Technology Mapping
Analog Place and Route
Digital Packing
Digital Placement
Digital Routing
<…there’s more…>
36
2014/10/27
Build Process
API Generation
Compilation
Configuration Generation
Configuration Verification
Development Files
Core Cypress Libraries (CyLib)
Registers, macros, types (cytypes)
Component addressing (cyfitter)
37
2014/10/27
Supported Compilers
Free Bundled compiler options
PSoC 5: GNU/CodeSourcery Sourcery G++™ Lite
No code size restrictions, not board-locked, no time limit
Fully integrated including full debugging support
GNU
Upgrade, more optimization/compiler-support options
PSoC 5: Keil RealView® Microcontroller Development Kit
Higher levels of optimization
Direct support from the compiler vendor
Upgrade Compiler Pricing
Set and managed by our 3rd party partner, Keil
Already own these compilers? No need to buy another license!
Keil RealView MDK ~$3,000-5,000
Integrated Debugger
JTAG and SWD connection
• All devices support debug
• MiniProg3 programmer / debugger
Control execution with menus, buttons and
keys
Full set of debug windows
• Locals, register, call stack, watch (4), memory (4)
• C source and assembler
• Components
Set breakpoints in Source Editor
38
2014/10/27
Debugger Windows
MiniProg3
• Program PSoC 1 devices
• Program/Debug PSoC 3 / PSoC 5 devices
• Standard 50mil connector
• nTRST/XRES pin is used as the device reset (XRES)
by default
2x5 50mil
ISSP/JTAG/SWD/
SWV/TracePort
ribbon cable and
connector
• nTRST is JTAG specific and rarely used
ISSP connector
39
2014/10/27
Review
You should now be able to:
• Follow the PSoC Creator Design Flow and develop projects
• Find and use the tools available within the software IDE
• Compile, build and program PSoC 5 applications
• Debug PSoC 5 applications
40