Transcript Altera PowerPoint Template

Timing constraints: Are they constraining
designs or designers?
Tom Spyrou
TAU 2015
3/2015
How do designers make timing
constraints?
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Focus first on flat or block level constraints
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Designers create clock, input and output arrival times based on a
system or block level specification
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Usually simple to create and don’t change too much
Easy to verify and modify
Multi-cycle paths
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Also created by hand from system or block specification
If one is missed and the path doesn’t show up in a timing report as critical it may never be
fixed. Some over-constraining.
Late SDC changes needed for paths that suddenly pop up and need to be fixed
 Not too scary to add these in late since the path is visible and the clocking easy to analyze
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False Paths
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Some are set pro-actively
Many are set by the user when an unwanted path shows up as critical
The complete set of false paths is never specified
Tools to do so fail from the complexity of the problem or from the size of the set of exceptions
and their affect on STA runtime and memory
Late SDC changes needed for paths that suddenly pop up and need to be fixed
 These are scary because someone has to sign in blood that the path is always false
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New additions to syntax for common
complex cases
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Use cases for path segmentation
 Study them and look for possibilities
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For example before –through many multi-cycle
paths were constrained with path segmentation
 Big step forward to have –through
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Clock Domain Crossings
 Propose new set_max_skew command
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CDC Transfer Constraining
Example: FIFO Write -> Read domains Stack Pointer transfer
– Gray coded transfers ensure 1 bit transitions
Need to control datapath delay to be low skew and low delay for
clock domain crossing (CDC) paths
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CDC Transfer Constraining
Many users set_false_path on this transfer
set_false_path -to [get_pins {*altera_std_synchronizer:*/d}]
– Cuts all setup & hold analysis on transfers between clocks A and B
Some users used Clock Groups to cut whole domain transfers
set_clock_groups -asynchronous -group {A} -group {B}
– Cuts all setup & hold analysis on transfers between clocks A and B
– Can’t selectively constrain some paths while leaving others “don’t care”
Placement constraints and the assumption of low clock skew allowed this work
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One example of many creative ways people use SDC
Began to fail in newer technologies with higher skew and local clocks routed through LABs
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Why failures started happening?
Improvements in timing driven P&R take greater liberty in placement and routing
of logic elements
Routing delay and skew are of no concern to the Fitter because of the false path
constraint
Higher Fmax demands for clock domains drive tighter timing requirement
Increased clock skew on highly utilized designs
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Desired Situation
Constrain both skew and total wire delay to keep this transfer
short, low-skew, and functionally correct for the needs of the
interface & system
– Constrain both clock and data skew together
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CDC Transfer Constraining - The New Way
The new way: Constrain datapath delay and total bus
skew with knowledge of the clocks involved
Important changes in Quartus II 15.0
– New constraint set_max_skew added
– New constraint set_net_delay added
– Lower precedence than set_false_path but higher
than everything else
– Smart options for set_max_skew, set_net_delay
Simple case is simple, but command is flexible
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SDC Precedence insertion
Now in Quartus15.0
Highest precedence
set_false_path (unchanged)
set_net_delay (raised)
set_max_skew (raised)
set_clock_groups (lowered)
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Lowest precedence
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New Exceptions
set_max_skew
[-fall_from_clock <names>]
[-fall_to_clock <names>]
[-from <names>]
[-from_clock <names>]
[-get_skew_value_from_clock_period <src_clock_period|dst_clock_period|min_clock_period>]
[-rise_from_clock <names>]
[-rise_to_clock <names>]
[-skew_value_multiplier <multiplier>]
[-through <names>]
[-to <names>]
[-to_clock <names>]
[<skew>]
set_net_delay
-from <names>
[-max] [-min]
[-from <names>]
[-to <names>]
<delay>
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Using New Options for set_max_skew on
CDC Busses
set_max_skew -from in_wr_ptr_gray*/q -to din_s1*/d \
-get_skew_value_from_clock_period min_clock_period
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