Transcript Chapter # 4

A Strange Counter
QA+
D
Q
QA
DB
D
Q
DC
QB
D
Q
QC
clk
Clock
QA
0
0
1
0
0
1
QB
0
1
1
0
1
1
QC
0
1
0
0
1
0
State 000
State 011
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State 110
State000
State 011
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A Strange Counter (Redrawn)
Combinational
Feedback Logic
DA
Next
State
DB
DC
D
Q
D
Q
D
Q
QA
QB
Current
State
(Output)
QC
clk
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EE 1210 - Logic System Design
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A Generalized Synchronous Circuit
Next
State
Current
State
State
FlipFlops
Comb.
Logic
For
Outputs
Outputs
Clock
Combinational
Logic
For Next State
Outputs may be:
The state itself
Some function of the state
The number of possible states is 2n, where n is the number of FlipFlops.
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EE 1210 - Logic System Design
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Analyzing a counter
Current State
FF Inputs
Next State
DA=QB+QC Q Q Q D D D Q + Q + Q +
A
B
C
A
B
C
A
B
C
0 0 0 0 1 1 0 1 1
DB=QAQB
DC=QB+QA
DA
D
Q
QA
clr
DB
D
Q
QB
clr
DC
D
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
QAQBQC
Q
QC
001
000
011
clr
reset
clk
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010
110
111
100
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101
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Step 1: Derive the State Transition Diagram
Count sequence: 000, 011, 100, 101, 010, 001,000,…
Step 2: State Transition Table
Current State Next State
QA
0
0
0
0
1
1
1
1
QB
0
0
1
1
0
0
1
1
QC
0
1
0
1
0
1
0
1
QA+ QB+ QC+
0 1 1
0 0 0
0 0 1
1 0 0
1 0 1
0 1 0
X X X
X X X
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000
011
001
100
010
101
Note the Don't Care conditions
EE 1210 - Logic System Design
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Custom Counter: Mapping to D FFs
Step 3: Choose Flipflop Type for Implementation
Figure out FF inputs that will cause appropriate state change
Current State Next State
QA
0
0
0
0
1
1
1
1
QB
0
0
1
1
0
0
1
1
QC
0
1
0
1
0
1
0
1
QA+ QB+ QC+
0 1 1
0 0 0
0 0 1
1 0 0
1 0 1
0 1 0
X X X
X X X
FF Inputs
DA
0
0
0
1
1
0
X
X
DB
1
0
0
0
0
1
X
X
DC
1
0
1
0
1
0
X
X
For D FF’s next
state is just the D
input: Q+  D
Next State Functions with D FF’s
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EE 1210 - Logic System Design
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Custom Counter: Finishing
Step 4: Make K-maps for each flipflop input and find final functions
DA
C 0
AB
00
01
0
0
C
DB
C 0
AB
1
0
00
01
1
1
0
C
1
0
0
B
A
11
X
X
10
1
0
B
A
DA=AC’ + BC
DC
C 0
AB
00
1
01
1
11
X
X
10
0
1
DB=A’B’C’ + AC
C
Pre
D
C’
A
Q
A’
B’
C’
A
C
GND
Pre
D
Q
X
10
1
0
B
Clr
C’
0
X
Reset
GND
0
11
A
Clr
1
B
A
GND
B
C
Pre
D
Q
C
Clr
DC= C’
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EE 1210 - Logic System Design
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Custom Counter: Remapping to T FFs
Step 3: Choose Flipflop Type for Implementation
Figure out FF inputs that will cause appropriate state change
Current State Next State
QA
0
0
0
0
1
1
1
1
QB
0
0
1
1
0
0
1
1
QC
0
1
0
1
0
1
0
1
QA+ QB+ QC+
0 1 1
0 0 0
0 0 1
1 0 0
1 0 1
0 1 0
X X X
X X X
FF Inputs
TA TB
0 1
0 0
0 1
1 1
0 0
1 1
X X
X X
TC
1
1
1
1
1
1
X
X
For T FF’s, we have to look at
the current state and the
next.
If the next state is different
from the current, then we
must toggle (T=1).
Next State Functions with T FF’s
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EE 1210 - Logic System Design
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Finishing with Toggle FFs
Step 4: Make K-maps for each flipflop input and find final functions
TA
C 0
AB
00
0
01
0
C
TB
C 0
AB
1
C
1
0
00
1
0
1
01
1
1
11
X
X
10
0
1
B
A
11
X
X
10
0
1
TA=C(A+B)
TC
C 0
AB
00
1
01
1
A
TB= A’C’ + B + AC
C
GND
B
A
B C
Pre
T
Clr
11
10
X
1
Reset
GND
A’
C’
B
A
C
Pre
T
Q
B
Clr
1
GND
1
‘1’
1
Pre
T
Q
C
Clr
B
A
Q
A
X
1
TC=1
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VHDL Counters
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY cnt IS
000
PORT(clk: IN STD_LOGIC;
011 A 001
reset: IN STD_LOGIC;
B
F
z: OUT STD_LOGIC_VECTOR(2 downto 0));
100C
E
END cnt;
010
ARCHITECTURE behavior OF cnt IS
D
101
Type state_type is (A,B,C,D,E,F);
SIGNAL state: state_type;
BEGIN
Declare possible states
PROCESS(reset,clk)
(A-F is six states)
BEGIN
if (reset=‘1’) then
state <= A;
z <=“000”;
Asynchronous reset to 000
elsif (rising_edge(clk))then
case state is
when A=> state <= B; z <= "011";
when B=> state <= C; z <= “100";
when C=> state <= D; z <= "101";
Here’s the counter…
when D=> state <= E; z <= “010";
when E=> state <= F; z <= “001";
when F=> state <= A; z <= "000";
END CASE;
end if;
end process;
END behavior;
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