Transcript DESIGN VERIFICATION

Design Verification
VHDL ET062G & ET063G Lecture 5
Najeem Lawal 2012
DESIGN VERIFICATION
OUTLINE
– Test Bench
– Clock generation
– Reading BMP
– Generating Control Signal
– Testing the result
Najeem Lawal, 2012
VHDL ET062G & ET063G
Lecture 5
2
ERROR MANAGEMENT IN VHDL
Assert statement
Syntax:
Assert <condition>
Report <message>
Severity <error_level> ;
Message and Error Level are displayed in the simulator console as text.
Assert statements can be both sequential and concurrent statements.
Assert statements should only be in the test-benches because there are not
synthesizable.
Najeem Lawal, 2012
VHDL ET062G & ET063G
Lecture 5
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ERROR MANAGEMENT IN VHDL
architecture ex of assert_ex is
Entity assert_ex is
port ( a,b : in std_logic;
q : out std_logic);
begin
assert a /= '1' or b /= '1'
report “a='1' and b='1' at the same time!”
end entity assert_ex;
architecture ex of assert_ex is
severity Warning;
P1 : process(a,b)
begin
if a ='1' and b = '1' then
assert false
report “a='1' and b='1'”;
end if
end process P1;
end architecture ex;
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Lecture 5
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TESTBENCHES IN VHDL
AT LEAST 3 ESSENTIAL COMPONENTS
– Unit Under Test UUT
– Stimuli generator
– Response tester
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5
TESTBENCHES IN VHDL
AT LEAST 3 ESSENTIAL COMPONENTS
– Unit Under Test UUT
• Your designs
• 4 bit adder
• Counter
• Sliding window
• Range sensor
• Edge detector
• Complete project
– Stimuli generator
– Response tester
Najeem Lawal, 2012
VHDL ET062G & ET063G
Lecture 5
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TESTBENCHES IN VHDL
AT LEAST 3 ESSENTIAL COMPONENTS
– Unit Under Test UUT
– Stimuli generator
• Many specialised stimuli generator
• Clocks, reset
• Control signals
• Data signals
• Models of sensors and actuator your UUT
connects to
– Response tester
Najeem Lawal, 2012
VHDL ET062G & ET063G
Lecture 5
7
TESTBENCHES IN VHDL
AT LEAST 3 ESSENTIAL COMPONENTS
– Unit Under Test UUT
– Stimuli generator
– Response tester
• Many specialised test modules
• Truth table
• Established values or controls status
• Waveform analysis
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TYPICAL TESTBENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
Closed entity - no port
It is the highest module
ENTITY test_Project_2010 IS
-- nothing here
-- no ports
-- this is the envelop of the universe
END entity test_Project_2010;
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VHDL ET062G & ET063G
Lecture 5
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EXAMPLE
ARCHITECTURE behavior OF test_Project_2010 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT edge_sobel_wrapper
PORT(
clk : IN std_logic;
fsync_in : IN std_logic;
rsync_in : IN std_logic;
pdata_in : IN std_logic_vector(7 downto 0);
fsync_out : OUT std_logic;
rsync_out : OUT std_logic;
pdata_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
SIGNAL clk : std_logic := '0';
SIGNAL fsync_in : std_logic := '0';
SIGNAL rsync_in : std_logic := '0';
SIGNAL pdata_in : std_logic_vector(7 downto 0) := (others=>'0');
…..
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Lecture 5
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EXAMPLE
To perform some
asynchronous functions
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: edge_sobel_wrapper PORT MAP(
clk => clk,
fsync_in => fsync_in,
rsync_in => rsync_in,
pdata_in => pdata_in,
fsync_out => fsync_out,
rsync_out => rsync_out,
pdata_out => pdata_out
);
Input clock, data & controls
And output
It’s good to have naming convention
Najeem Lawal, 2012
VHDL ET062G & ET063G
Lecture 5
img_read : entity work.img_testbenchSimilar clock
port map (
as UUT
pclk_i => clk,
reset_i => reset,
fsync_i => fsync_out,
Mimics a
rsync_i => rsync_out,
camera
pdata_i => pdata_out,
cols_o
=> open,
rows_o
=> open,
col_o
=> open,
row_o
=> open,
fsync_o => fsync_in,
Mimics a
rsync_o => rsync_in,
monitor
pdata_o => pdata_in);
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EXAMPLE
Clock is just a signal that toggles between
‘0’ and ‘1’ at a predefined rate.
clock_generate: process (clk)
constant T_pw : time := 50 ns;
-- Clock period is 100ns.
begin -- process img
10 MHz clock.
if clk = '0' then
Because the camera
clk <= '1' after T_pw, '0' after 2*T_pw;
end if;
end process clock_generate;
50 % duty
is 10 MHz
Default value of clock is ‘0’
reset <= '1', '0' after 60 ns;
END;
Time long enough to do
a few house cleaning and data initialization
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HINTS
• The UUT IS SELF SUFFICIENT AND
SYNTHESISABLE
• IT CONNECTS TO OTHER DEVICES THROUGH
THE FPGA IO PINS
• CONTAINTS ALL PORTS AND GENERICS FOR
IMPLEMENTATION
• CLOCKS SHOULD BE CLOSE TO FINAL
IMPLEMENTATION TIMING REQUIREMENTS
• YES, WE NEED RESET TO KICK START US
FROM OR BRING US TO KNOW STATES
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IMG_TESTBENCH
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
use std.textio.all;
entity img_testbench is
port (
pclk_i
: in std_logic;
reset_i
: in std_logic;
fsync_i
: in std_logic;
rsync_i
: in std_logic;
pdata_i
: in std_logic_vector(7 downto 0);
cols_o
: out std_logic_vector(15 downto 0);
rows_o
: out std_logic_vector(15 downto 0);
col_o
: out std_logic_vector(15 downto 0);
row_o
: out std_logic_vector(15 downto 0);
rsync_o
: out std_logic;
fsync_o
: out std_logic;
pdata_o
: out std_logic_vector(7 downto 0) );
end img_testbench;
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Lecture 5
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IMG_TESTBENCH
How to read image files a stream of 8 bit
...
architecture main of img_testbench is
type ByteT is (c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,
c19,c20,c21,c22,c23,c24,c25,c26,c27,c28,c29,c30,c31,c32,c33,c34,
--subtype Byte is ByteT;
type ByteFileType is file of Byte;
file infile
: ByteFileType open read_mode is "test.bmp";
file outfile : ByteFileType open write_mode is "result_08bits.bmp";
A new type that can
read 8-bit character
from file.
…
Najeem Lawal, 2012
VHDL ET062G & ET063G
Lecture 5
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IMG_TESTBENCH
...
-- integer to bit_vector conversion
function int2bit_vec(A: integer; SIZE: integer) return BIT_VECTOR is
variable RESULT : BIT_VECTOR(SIZE-1 DOWNTO 0);
variable TMP
: integer;
begin
TMP := A;
for i in 0 to SIZE - 1 loop
if TMP mod 2 = 1 then RESULT(i) := '1';
else RESULT(i) := '0';
end if;
TMP := TMP / 2;
end loop;
return RESULT;
end;
A function that converts
integers to bits vector of a
given size.
Subprograms in VHDL
- procedure?
- function?
…
Najeem Lawal, 2012
VHDL ET062G & ET063G
Lecture 5
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IMG_TESTBENCH
...
begin -- main
img_read : process (pclk_i)
variable pixelB : Byte;
variable pixelG : Byte;
variable pixelR : Byte;
variable pixel : Byte;
variable pixel1 : REAL;
variable cols : std_logic_vector(15 downto 0);
variable rows : std_logic_vector(15 downto 0);
variable col : std_logic_vector(15 downto 0);
variable row : std_logic_vector(15 downto 0);
variable cnt : integer;
variable rsync : std_logic := '0';
variable stop : std_logic;
Store RGB pixel values
Effective pixel
value
Counter for
blanking
When to
stop
begin -- process img_read
if (reset_i = '1') then
pdata_o
col
row
For reading from the BMP File
How many rows, columns
which row and column are we in
the image file
Valid pixel indicator
<= (others => '0');
:= (others => '0');
:=
(others => '0');
…
Najeem Lawal, 2012
VHDL ET062G & ET063G
Lecture 5
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IMG_TESTBENCH
...
for i in 0 to 53 loop -- read header infos
read(infile, pixel);
write(outfile, pixel);
case i is
when 18 =>
-- 1st byte of cols
cols(7 downto 0 ) := To_Stdlogicvector(int2bit_vec(ByteT'pos(pixel), 8));
when 19 =>
-- 2nd byte of cols
cols(15 downto 8) := To_Stdlogicvector(int2bit_vec(ByteT'pos(pixel), 8));
when 22 =>
-- 1st byte of rows
rows(7 downto 0 ) := To_Stdlogicvector(int2bit_vec(ByteT'pos(pixel), 8));
when 23 =>
-- 2nd byte of rows
rows(15 downto 8) := to_Stdlogicvector(int2bit_vec(ByteT'pos(pixel), 8));
when 24 =>
-- do important things
cols_o <= cols;
rows_o <= rows;
cols
:= cols - 1;
rows
:= rows - 1;
when others =>
null;
end case;
end loop; -- i
Assign output
Assign upper limit
of internal counters
…
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VHDL ET062G & ET063G
Lecture 5
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BMP FILE FORMAT
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VHDL ET062G & ET063G
Lecture 5
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IMG_TESTBENCH
...
rsync := '1';
cnt
:= 10;
stop := '0';
elsif (pclk_i'event and pclk_i = '1') then
rsync_o <= rsync;
if rsync = '1' then
if row = "0000000000000000" and col = "0000000000000000" then
fsync_o <= '1';
else
fsync_o <= '0';
end if;
…
Najeem Lawal, 2012
VHDL ET062G & ET063G
Lecture 5
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IMG_TESTBENCH
...
if stop = '0' then
read(infile, pixelB); -- B
read(infile, pixelG); -- G
read(infile, pixelR); -- R
pixel1 := (ByteT'pos(pixelB)*0.11) + (ByteT'pos(pixelR)*0.3) + (ByteT'pos(pixelG)*0.59);
pdata_o
<= CONV_STD_LOGIC_VECTOR(INTEGER(pixel1), 8);
col_o
<= col;
row_o
<= row;
end if;
…
Najeem Lawal, 2012
VHDL ET062G & ET063G
Lecture 5
21
IMG_TESTBENCH
...
if col = cols then
col
:= (others => '0');
rsync := '0';
if row = rows then
File_Close(infile);
stop := '1';
else
row := row + 1;
end if;
-- row
else
col := col + 1;
end if;
-- col
…
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640 clk
640 clk
rsync = ‘1’
Where are we in the image
10 clk
rsync = ‘0’
VHDL ET062G & ET063G
Lecture 5
rsync = ‘1’
22
IMG_TESTBENCH
...
else
-- rsync
if cnt > 0 then
cnt
:= cnt -1;
else
cnt
:= 10;
rsync := '1';
end if;
pdata_o <= (others => 'X');
end if; -- rsync
…
Najeem Lawal, 2012
VHDL ET062G & ET063G
Lecture 5
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IMG_TESTBENCH
...
if rsync_i = '1' then
write(outfile, ByteT'val(ieee.numeric_std.To_Integer(ieee.numeric_std.unsigned(pdata_i)))); --, pixel);
write(outfile, ByteT'val(ieee.numeric_std.To_Integer(ieee.numeric_std.unsigned(pdata_i)))); --, pixel);
write(outfile, ByteT'val(ieee.numeric_std.To_Integer(ieee.numeric_std.unsigned(pdata_i)))); --, pixel);
end if; -- rsync_i
end if; -- clk
end process img_read;
end main;
…
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Lecture 5
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RANGE SENSOR
SRF05 HTTP://WWW.ROBOTSTOREHK.COM/SENSORS/DOC/SRF05TECH.PDF
– 10us pulse to the Trigger input
– 50ms period between each Trigger pulse
– Mode 1 recommended
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PROJECT IMPLEMENTATION
CONTROLLER IS FPGA
– System Clock and
Exposure are generated
– Understand timing
diagrams and implement
the project.
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SLIDING WINDOW
– An image is read from left to
right and top to bottom
• sliding
column
row
– Given an algorithm with many
tasks
O(x,y) = F(x,y) x I(x,y)
in
A)
– Some of the task are
neighbourhood oriented
• sliding window
• N x M sliding window.
• N and M are odd numbers
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VHDL ET062G & ET063G
p1
p2
p5
p3
p6
p4
p7
Sliding window
B)
Task
Image filter
27
out
SLIDING WINDOW
Neighbourhood p11 p12 p13
data
p21 p22 p23
p31 p32 p33
a)
b)
Linebuffers
In
data
...
Suggested implementation
architecture
1. linebuffers
2. Boundary controller
3. Pixel switch
4. Filter function
5. Output synchronisation
SLWC
Window
ctrl
Neighbourhood
output
(2a)
p11 p12 p13
p21 p22 p23
p31 p32 p33
Line buffer
d
p33
VHDL ET062G & ET063G
Sync.
Pixel
switch
(2b)
dpixel
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Image filter
function
Out
data
Line buffer
d
p32
d
p31
p23
28
d
d
p22
p21
p13
d
p12
p11
SLIDING WINDOW
W
ω
I
width
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height
– At the image edges
– There are invalid pixel
– How do you build a valid
neighbouthood of pixels around edge
pixels?
– 3 alternatives
• Avoid processing edge pixels
• Copy centre pixel to the invalid
pixel locations
• Reflections. Default to 0 or 255
QUESTIONS
ABOUT FPGA / VHDL
ABOUT VGA DISPLAY / TIMING
ABOUT IMAGE SENSOR TIMING
ABOUT RANGE SENSOR
ABOUT LINE BUFFERS
ABOUT MEMORIES & COUNTERS
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Lecture 5
30
END OF LECTURE 5
OUTLINE
– Test Bench
– Clock generation
– Reading BMP
– Generating Control Signal
– Testing the result
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VHDL ET062G & ET063G
Lecture 5
31