Transcript CDA 3101 Spring 2001 Introduction to Computer Organization

CDA 3101
Summer 2007
Introduction to Computer Organization
Multiplication
14 June 2007
Multiplication
• More complicated than addition
– Accomplished via shifting and addition
– Requires more time and chip area
• 3 versions of pencil-and-paper algorithm
0010 (multiplicand)
__x_1011 (multiplier)
0010 1 -> copy & shift
0010
1 -> copy & shift
0000
0 -> shift
0010
1 -> copy & shift
00010110 Sum Partial Products
.
First Version (V.1)
0010
1011
00000010
00000100
00001000
00010000
00010110
V.1: Hardware
Multiplicand (64 bits)
Shift left
Multiplier (32 bits)
64-bit ALU
Shift right
Multiplier0
Product (64 bits)
Write
Control test
Second Version (V.2)
Start
Multiplicand
32 bits
Multiplier0 = 1
Multiplier
Shift right
32-bit ALU
1. Test
Multiplier0
Multiplier0 = 0
32 bits
Product
Shift right
Write
Control test
1a. Add multiplicand to the left half of
the product and place the result in
the left half of the Product register
64 bits
2. Shift the Product register right 1 bit
Product
Multiplier0
1
1
0
1
00000000
00100000
00110000
00011000
00101100
3. Shift the Multiplier register right 1 bit
00010000
00011000
00001100
00010110
32nd repetition?
No: < 32 repetitions
Yes: 32 repetitions
Done
Final Version (V.3)
Multiplicand
Start
32bits
Product0 = 1
1. Test
Product0
Product0 = 0
32-bit ALU
Product
Shift right
Write
Control
test
1a. Add multiplicand to the left half of
the product and place the result in
the left half of the Product register
64bits
2. Shift the Product register right 1 bit
Product
00001011
00101011
00110101
00011010
00101101
32nd repetition?
00010101
00011010
00001101
00010110
No: < 32 repetitions
Yes: 32 repetitions
Done
Summary
• Unsigned multiplication
– Generate one partial product for each digit in
the multiplier
0
If multiplier digit = 0
– Partial product =
Multiplicand
If multiplier digit = 1
– Total product = sum of (left shifted) partial
products
– The multiplication of two n-bit binary integers
results in a product of up to 2n bits in length
General View
1011 Multiplicand (11)
Multiplicand
M31
...
x 1101 Multiplier
M0
Product
C
Add
32-bit
ALU
Shift
right
C
A31
. . . A0 Q31
Control
...
(13)
Q0
Multiplier
(143)
A
Q
M
Initial values 0
0000
1101
1011
1
Add
Shift
0
0
1011
0101
1101 1011
1110 1011
2
Shift
0
0010
1111
3
Add
Shift
0
0
1101
0110
1111 1011
1111 1011
4
Add
Shift
1
0
0001
1000
1111 1011
1111 1011
1011
Signed Arithmetic
• Signed addition and subtraction
– Treat operands as unsigned numbers
– Use the same algorithm/hardware used for the
corresponding unsigned operations
Unsigned
9
Signed
-7
+ 0011
3
3
1100
12
-4
1001
• Cannot do this for multiplication!
Example
1011
x 1101
10001111
Unsigned
11
13
Signed
-5
-3
143
-113
• Partial solution for negative multiplicands
1001 (9)
1001 (-7)
x 0011 (3)
x 0011 (3)
00001001 1001 x 20
11111001 (-7) x 20 = (-7)
00010010 1001 x 21
11110010 (-7) x 21 = (-14)
00011011 (27)
11101011 (-21)
• No straightforward solution if multiplier is negative
Negative Multiplier
• The bits of the multiplier no longer correspond to
the partial products
• Example: (-3) = 1101
– The partial products would be generated based on that
representation of the multiplier, i.e.:
1: - 1 x 20
0: - 0 x 21
1: - 1 x 22
1: - 1 x 23
– Instead, the partial products should be generated using
the following powers of 2:
- 1 x 20
- 1 x 21
Booth’s Algorithm
A
0, Q-1
0
M
Multiplicand
Q
Multiplier
Count
n
START
= 10
A
Q0,Q-1
= 01
= 00
= 11
A- M
A
A+M
Arithmetic shift right:
A, Q, Q-1
Count
Count - 1
No
Count = 0
?
Yes
END
Booth’s Hardware
Multiplicand
M31
...
32-bit
ALU
M0
Add / Subtract
Control
SRA
A31
. . . A0 Q31
...
Q0 Q-1
Multiplier
Example
7
x 3
A
Initial values
(0 1 1 1)
(0 0 1 1)
Q
Q-1
M
0000
0011
0
0111
1001
1100
0011
1001
0
1
0111 A = A - M
0111 Shift
1
1110
0100
1
0111 Shift
2
0101
0010
0100
1010
1
0
0111 A = A + M
0111 Shift
3
0001
0101
0
0111 Shift
4
Proof: Positive Multiplier
• First, consider a simple positive multiplier
0 0 0 1 1 1 1 0 (one block of 1s surrounded by 0s)
M x (0 0 0 1 1 1 1 0)
= M x (24 + 23 + 22 + 21)
= M x (16 + 8 + 4 + 2)
5 4 3 2 1 0
= M x 30
• Notice: 2n + 2n-1 + . . . + 2n-k = 2n+1 – 2n-k
=> M x (0 0 0 1 1 1 1 0) = M x (25 - 21)
• Both’s algorithm conforms to this scheme:
– Subtracts when beginning of 1 block is found (1-0)
– Adds when end of the block is encountered (0-1)
• This scheme extends to any number of 1 blocks
Proof: Negative Multipliers
• Representation of a negative number (X):
{ 1 xn-2 xn-3 . . . x1 x0 }
• X = -2n-1 + xn-2*2n-2 + xn-3*2n-3 . . . x0*20
• Assume the leftmost 0 is in the kth position
Representation of X = { 1 1 1 … 10 Xk-1 … X0}
X = -2n-1 + 2n-2 . . . 2k+1 + xk-1*2k-1 . . . x0*20
-2n-1 + 2n-2 + … + 2k+1 = -2k+1
X = -2k+1 + xk-1*2k-1 . . . x0*20
(1-0) transition occurs and a subtraction takes place
MIPS Multiplication
• Special purpose registers for the result (Hi, Lo)
• Two multiply instructions
– Mult: signed
– Multu: unsigned
• mflo, mfhi – move contents from Hi, Lo to
general purpose registers (GPRs)
• No overflow detection in hardware
=> Software overflow detection
• Hi must be 0 for multu or the replicated sign of Lo for
mult
Conclusions
•
•
•
•
Multiplication => Shift-and-add
Unsigned mult = Signed mult
Booth’s Algorithm used for signed mult
MIPS has special registers (Hi,Lo) and two
instructions (mult, multu)
• Think:
Weekend! 