Transcript Gates and Combinational Logic

Binary Multipliers
The key trick of multiplication is memorizing a digit-to-digit table…
Everything else was just adding
×
0
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
0
0
0
0
1
0
1
2
3
4
5
6
7
8
9
2
0
2
4
6
8
10
12
14
16
18
3
0
3
6
9
12
15
18
21
24
27
4
0
4
8
12
16
20
24
28
32
36
5
0
5
10
15
20
25
30
35
40
45
6
0
6
12
18
24
30
36
42
48
54
7
0
7
14
21
28
35
42
49
56
63
8
0
8
16
24
32
40
48
56
64
72
9
0
9
18
27
36
45
54
63
72
81
×
0
1
0
0
0
1
0
1
You’ve got to be
kidding… It can’t
be that easy
Reading: Study Chapter 3.
Comp 411 – Spring 2008
02/26/2008
L11 – Multiplication Division 1
Binary Multiplication
The “Binary”
Multiplication
Table
X 0
Hey, that
looks like an
AND gate
1
0 0 0
1
0
Binary multiplication is implemented using
the same basic longhand algorithm that
you learned in grade school.
A3
x B3
1
AjBi is a “partial product”
A3B2
A2
B2
A1
B1
A0
B0
A3B0 A2B0 A1B0 A0B0
A3B1 A2B1 A1B1 A0B1
A2B2 A1B2 A0B2
+ A3B3 A2B3 A1B3 A0B3
Multiplying N-digit number by M-digit number gives (N+M)-digit result
Easy part: forming partial products (just an AND gate since BI is either 0 or 1)
Hard part: adding M, N-bit partial products
Comp 411 – Spring 2008
02/26/2008
L11 – Multiplication Division 2
Multiplication: Implementation
Start
Multiplicand
Shift left
64 bits
Multiplier0 = 1
Multiplier
Shift right
64-bit ALU
Multiplier0 = 0
1. Test
Multiplier0
32 bits
Product
Write
1a. Add multiplicand to product and
place the result in Product register
Control test
64 bits
2. Shift the Multiplicand register left 1 bit
3. Shift the Multiplier register right 1 bit
32nd repetition?
No: < 32 repetitions
Yes: 32 repetitions
Done
Comp 411 – Spring 2008
02/26/2008
L11 – Multiplication Division 3
Second Version
Start
Multiplicand
32 bits
Multiplier0 = 1
Multiplier
Shift right
32-bit ALU
Multiplier0 = 0
1. Test
Multiplier0
32 bits
Product
Shift right
Write
1a. Add multiplicand to the left half of
the product and place the result in
the left half of the Product register
Control test
64 bits
2. Shift the Product register right 1 bit
3. Shift the Multiplier register right 1 bit
32nd repetition?
No: < 32 repetitions
Yes: 32 repetitions
Done
Comp 411 – Spring 2008
02/26/2008
L11 – Multiplication Division 4
Example for second version
Iteration
Step
Multiplier
Multiplicand
Product
0
Initial
1011
0010
0000 0000
1
Test true
shift right
1011
0101
0010
0010 0000
0001 0000
2
Test true
shift right
0101
0010
0010
0011 0000
0001 1000
3
Test false
shift right
0010
0001
0010
0001 1000
0000 1100
4
Test true
shift right
0001
0000
0010
0010 1100
0001 0110
Comp 411 – Spring 2008
02/26/2008
L11 – Multiplication Division 5
Final Version
Start
Multiplicand
32 bits
Product0 = 1
1. Test
Product0
Product0 = 0
32-bit ALU
Product
Shift right
Write
Control
test
1a. Add multiplicand to the left half of
the product and place the result in
the left half of the Product register
64 bits
2. Shift the Product register right 1 bit
The trick is to use the lower half of the product
to hold the multiplier during the operation.
32nd repetition?
No: < 32 repetitions
Yes: 32 repetitions
Done
Comp 411 – Spring 2008
02/26/2008
L11 – Multiplication Division 6
What about the sign?
Positive numbers are easy.
How about negative numbers?
(see Booth coding in textbook)
Comp 411 – Spring 2008
02/26/2008
L11 – Multiplication Division 7
Faster Multiply
A1 & B
A0 & B
A2 & B
A2 & B
A31 & B
P32-P63
Comp 411 – Spring 2008
02/26/2008
P31
P2
P1
P0
L11 – Multiplication Division 8
Simple Combinational Multiplier
tPD = 10 * tPD,FA
A
Co
not 16
HA
A
B
Co
S
HA
S
A
B
Co
HA
S
A
B
Co
HA
B
S
tPD = (2*(N-1) + N) * tPD,FA
Components
N * HA
N(N-1) * FA
The Logic
of a
HalfAdder
CO
AB
S
NB: this circuit only
works for nonnegative
operands
Comp 411 – Spring 2008
02/26/2008
L11 – Multiplication Division 9
Carry-Save Combinational Multiplier
These
Adders
can be
removed,
and the
AND gate
outputs
tied
directly to
the Carry
inputs of
the next
stage.
Observation: Rather
than propagating the
sums across each row,
the carries can instead
be forwarded onto the
next column of the
following row
This small
improvement
in
performance
hardly seems
worth the
effort,
however, this
design is
easier to
pipeline.
tPD = 8 * tPD,FA
tPD = (N+N) * tPD,FA
Components
N * HA
N2 * FA
Comp 411 – Spring 2008
02/26/2008
L11 – Multiplication Division 10
Division
Start
1. Subtract Divisor from the
Remainder leave the result
in the Remainder
>=0
Test
Remainder
<0
Restore Remainder by adding Divisor
Shift Quotient to the left
set its rightmost bit = 0
Shift Quotient to the left
set its rightmost bit = 1
Shift Divisor Register right 1 bit
Repeat 33
times
Comp 411 – Spring 2008
02/26/2008
L11 – Multiplication Division 11