Transcript Alternative Chemistries for Wafer Patterning and PECVD

MTL: The Microsystems
Technology Laboratories at MIT
Prof. Martin A. Schmidt
Massachusetts Institute of Technology
Microsystems Technology Laboratories - MIT
MTL - The Facilities
• Integrated Circuits Laboratory
– Class 10 - 2800 sq.ft. (6")
– 1.25 micron CMOS baseline process
• Technology Research Laboratory
– Class 100 - 2200 sq.ft. (6")
– Flexible Process Environment
• Exploratory Materials Laboratory
– Class 1000 - 2000 sq.ft.
– Thin Film Process Facility
• IC Design Laboratory
– Foundry IC Processes
Microsystems Technology Laboratories - MIT
MTL Technology: A Tour of Scale
Gyroscopes
Displays
Transistors
Microengines
mm
mm
nm
Microchemical
Plants
Connectors
Low Power IC
Microsystems Technology Laboratories - MIT
Nanotips
Lamination of Extruded 2-D Shapes
Valve
Controller
High
Pressure
Low
Pressure
Piezo
Valve
Valve
Electrical
Power
Microsystems Technology Laboratories - MIT
Opportunities
• Rapid 2-D Extrusion
– Plastics, Silicon, Ceramics
– First-Pass Success
• Process modeling and tool characterization
– Lower Cost
• Transition from semiconductor mindset to machine
tool mindset
• Aligned Bonding of Chips
– Transition from optical to mechanical/chemical
• Self-assembly
• LEGO (A. Slocum)
Microsystems Technology Laboratories - MIT