Transcript Research Projects Overview

On the Need for Statistical
Timing Analysis
Farid N. Najm
University of Toronto
[email protected]
Introduction
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Increased process variability leads to chip timing
variability and lower timing yield
Traditionally, corner-analysis (worst-case files) has been
used to manage timing variability
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Statistical Static Timing Analysis (SSTA) has been
proposed as an alternative approach
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Corner analysis has some disadvantages
SSTA has its own disadvantages
Perhaps an alternative “best of both worlds” approach
is required:
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Use statistical analysis to better choose the corners or the
margins to be used in a traditional STA approach
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Generation of Corner-Case Files
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Principal Components Analysis
de-correlates SPICE parameters
and captures bulk of variations
Process parameter corners
chosen to maximize MOSFET
performance yield
Extract I-V curves
from extensive
measurements
Deduce SPICE parameters
from measured data
Use PCA to deduce
corner-case SPICE models
Use Response Surface Modeling
(RSM) for corner-case analysis
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Disadvantages of Corner Analysis
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Some disadvantages:
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Corners should maximize circuit yield, not device yield
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Goal is to bracket most (say, 99.73%) of what?
individual process variable space?
2. typical transistor strength?
3. typical gate/cell delay?
4. overall circuit performance?
1.
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There are too many corners
Cannot take care of within-die variations
Corner analysis is overkill
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Ideally, one would like #4, but traditionally go with #2
One is capturing much more yield (performance spread) than
one really needs to
Cannot determine how robust the design is
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Too Many Corners
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With more process parameters, the number of process
corners increases exponentially
However, there have been recent proposals to reduce
the number of corners to be considered
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Corner clustering (Sengupta et al., ISQED-04)
This method also allows one to choose corners so as to bracket
circuit performance, instead of device performance
 Quadratic
circuit response, RSM: g(X) = a + bX + XTBX
 Solution: X vector that minimizes and maximizes g(X)
 Cluster corners that are close in the parameter space
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Case Files & Intra-Die Variations
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Traditional corner analysis cannot take care of withindie variations
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Heuristic techniques are used within some traditional STA
tools to approximately take care of within-die effects
The crux of the problem lies in the systematic
within-die variations
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Random within-die variations “cancel out” on a path
 They
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don’t exactly cancel out, but their net result is reduced
The overall impact of within-die variations on circuit
delay arguably remains small compared to die-to-die
variations (S. Samaan, ICCAD-04)
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Too Much Guardbanding
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Corner analysis becomes “overkill” when the implicit
yield target becomes too large
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Not always the case in corner analysis!
Assume that a nominal value of yield is what covers
the ± 3 of a standard normal distribution: Y0 = 99.73%
 Whether corner analysis is overkill or not depends on
the performance metric
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If g(X) = Xi (i = 1 ,…, n), then Y  (3n1/2) - (-3n1/2) > Y0
 Setting
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If g(X) = max (Xi) then Y  n(3) - n(-3) < Y0
 Setting
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Xi at ± 3 is overkill
Xi at ± 3 is NOT overkill
It also depends on the shape of the acceptability region
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Assessment
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The straightforward nature of corner-case analysis has
made it the method of choice in industry
It has some limitations:
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Need to determine corners based on circuit performance
Location of corners depends on acceptability region
Need to reduce the number of corners to be covered
Cannot determine how robust the design is
Nevertheless, criticisms do not dismiss this approach
altogether
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Statistical Timing Analysis
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Recently, “Statistical Static Timing Analysis” (SSTA)
has been proposed
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Deal with circuit timing uncertainty
An alternative to corner analysis
Basic Idea:
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Propagate delay distributions, instead of deterministic delays,
in the timing graph
 Compute
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node and path delay distributions
Estimate the distribution of circuit delay as the joint
distribution of path delays
Find the chip timing yield from circuit delay distribution
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Statistical Timing Analysis
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How to handle different types of delay correlations ?
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How to propagate distributions in the timing graph ?
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The statistical MAX function
Statistical SUM function
What types of distributions to use ?
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Within-die systematic correlation
Path sharing (reconvergent fanout)
Dependence on global sources of variations
Gaussian, or arbitrary distributions ?
Distinct trends:
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Block-based statistical timing
Path-based statistical timing
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Block-Based SSTA
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Propagate distributions of arrival times in the timing
graph of the block to get circuit delay distribution
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Path distributions are available only indirectly
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The MAX Operation
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Arrival times are “MAX-ed” at the nodes of the graph
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Circuit delay distribution is obtained on the primary outputs
The various methods differ in:
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How the MAX operation is performed
Assumptions on the nature of the distributions (Gaussian/not)
Whether and how correlation is taken care of
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Overview: Block-Based Methods
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A key difference among block-based methods lies in
whether delays are assumed Gaussian or arbitrary
Two Gaussian approaches both use decomposition, but
differ in what underlying variables are used
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Visweswariah et al. derive correlations from global sources of
variation
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Sapatnekar et al. perform PCA on the spatial correlations
Two non-Gaussian approaches differ in the propagation
algorithm of arrival times
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Blaauw et al. use conservative bounds on delay distributions
Devgan et al. use piece-wise linear approximations
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Path-Based Methods
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Path delay distributions are expressed as functions of
the underlying sources of variation
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Circuit delay distribution is obtained from the joint
probability of path delays
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Gate delay distributions are added to get path delay
distribution
Literature by: Nassif, Jess, Orshansky, Bowman
Circuit delay = MAX(all path delays)
Flow:
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Enumerate all critical paths
Estimate path delay distributions
Use multi-dimensional integration to combine all paths
Estimate the timing yield
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Assessment
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The problem of propagating delay distributions along
paths or through blocks is now “solved”
Yet, this does not mean that SSTA is now “solved”!
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Key problems in the proposed methods of SSTA
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What does one do with all these distributions?!
Unless if the full chip is “timed” flat, require change in
methodology: cannot “time” a path or block in isolation
Correlation handling requires layout information, hence cannot
be used pre-placement during circuit design/optimization
Not clear how to get correlation statistics from the process; a
disconnect between process and EDA
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Practical SSTA
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Desirable features of a practical SSTA approach:
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One can envision three types of SSTA:
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Must require minimal statistical process data
Must account for correlated and uncorrelated variations
Must be usable pre-placement to enable design optimization
Must be applicable to “early design” with uncertain circuitry,
in order to allow one to time a path/block in isolation
Process-specific, not design-specific, during early design
Design-specific, not placement-specific, during circuit design
Placement-specific, during physical design
A mix of the three types of SSTA would constitute a
practical framework for managing timing variability
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An Early Design Approach
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A recent approach (Najm and Menezes, DAC-04) is
applicable during early design
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Employ notion of generic paths to develop an approach which
is process-specific, not design-specific
The ability to handle early (uncertain) design is key to
being able to time a path/block in isolation!
Shift focus from the specific design to a design type
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What are a typical transistor/gate in this technology?
What is a typical path length in this class of design?
Assume the circuit or block consists of a large number of such
“generic paths”
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Overview
"Summary" design
style information:
- generic paths
- cell delay models
"Summary"
process files
Yield-targeted timing
margins for timing
verification under nominal
parameter values
Analysis
Chip timing
yield
Yield-targeted corner-case
files for use in STA
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Conclusions
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Process variability is a key factor of timing yield loss
and deterioration of circuit performance
Traditional corner analysis has some limitations, but
they are not insurmountable
Statistical timing analysis is being proposed as an
alternative, but it has its own limitations
Perhaps one can have it both ways
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Combine features of statistical analysis and corner-case files
Derive virtual corners and timing margins for a yield-aware
timing verification
This continues to be an active research topic
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