Transcript ECE-L304 Lecture 3

ECE-L304 Lecture 6
Review of Step 5
Introduction to Step 6 and 7
Final Lecture
Quiz Next Week
Up to now
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ADC is running
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DAC is running
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What is your sampling rate?
What is your resolution?
555 Timer is running (or close to running)
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What is the frequency and duty cycle?
ECE-L304 Lecture 7
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The final stretch - What
remains?
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Build 17 bit address generator for RAM
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Using 2 8 bit counters + ?
Build Control Circuitry to:
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Take a reading on the ADC
Store it to RAM
Once RAM is filled, output recorded
waveform
ECE-L304 Lecture 7
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Step 6 and 7
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Prelab
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Read the datasheets for the 74LS08 AND
gate, 74LS112 JK flipflop, 74LS590 8-bit
counter
Complete the Step 6 Prelab Worksheet
Review RAM and ADC control logic
ECE-L304 Lecture 7
4
Project Circuit
Progress to Date
8
ADC
8
RAM
Address
Gen
R/W
Control
ECE-L304 Lecture 7
DAC
Clock
5
Project Circuit
Step 7 Blocks
8
8
RAM
ADC
?
ADC
Control
DAC
2
17
R/W
Control
Address
Gen
ECE-L304 Lecture 7
Clock
6
Step 6
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Part 1
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Assemble the 16-bit address generator
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Design and build a circuit that will provide a
17th bit
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Place the circuitry according to your floorplan
Use the 555 counter as the clock for now
This step is required to get full hardware credit
Confirm functionality using the logic
analyzer
ECE-L304 Lecture 7
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Step 6
74LS590 Description
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8-Bit Counter With Register
Parallel Register Outputs
Choice Of 3 State Or Open Collector
Register Outputs
Guaranteed Counter Freq DC To 20
MHz
ECE-L304 Lecture 7
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Step 6
74LS590 Description
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Multi-chip applications
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“For cascading, a ripple carry output RCO is
provided. Expansion is easily accomplished for
two stages by connecting RCO of the first stage to
CCKEN of the second stage. Cascading for larger
count chains can be accomplished by connecting
RCO of each stage to CCK of the following stage.”
ECE-L304 Lecture 7
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Step 6
Cascaded 74LS590 Chips
LO
CLK
HI
G
LO
G
CCLK
CCLK
CCLKEN RCO
A7
RCLK
CCLKEN RCO
A7
RCLK
CCLR
A7
A6
A6
A5
A15
A6
A14
A5
A5
A13
A4
A4
A4
A12
A3
A3
A3
A11
A2
A2
A2
A10
A1
A1
A1
A9
A0
A0
A0
A8
HI
ECE-L304 Lecture 7
CCLR
10
Step 6
74LS590 Description
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“Both the counter and register clocks
are positive edge triggered. If the user
wishes to connect both clocks together,
the counter state will always be one
count ahead of the register.”
ECE-L304 Lecture 7
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Part 2 - Measure AND Time
Delay
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Wire the clock signal into two AND gates in
series to create a delay
Measure the delay and use this signal as the
input for your control circuitry
Use the oscilloscope to measure delay by
placing the input and output signals on the
screen simultaneously, trigger on the input
signal and use the cursors to measure the
delay between edges
ECE-L304 Lecture 7
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Step 6 Prelab
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Analyze the control circuit used in the
Step 4 simulation
Q
from Address
Generator
TC = Terminal Count
Q
ECE-L304 Lecture 7
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Step 6 Prelab
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Graph the expected outputs
1
Q
0
1
Qbar
RE = Read Enable
OE = Output Enable
WE = Write Enable
0
1
CLK
0
1
RE (OE)
0
1
WE
Draw these curves
0
ECE-L304 Lecture 7
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Step 6 Prelab
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In your Prelab Workbook
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Sketch the schematic
Sketch your control circuitry and timing
diagrams needed to control circuit
ECE-L304 Lecture 7
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What should the circuit do?
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The circuit should have two stages
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1- Take 2^17 readings from the ADC and store
then in the RAM
2- Take the ADC offline and write the recorded
signals from the RAM to the bus for output
Note - The ADC output and the RAM input/output
are all on the same bus, meaning that the ADC
cannot write outputs to the bus at the same time
as the RAM
ECE-L304 Lecture 7
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Part 3 - Control Circuitry
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First - decide which signals are involved in
the control circuitry
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555 Timer
ADC controls
RAM controls
Second - create a timing diagram that
describes what the signals need to look like in
order to control the circuit properly
ECE-L304 Lecture 7
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Board Center Connectors
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ADC Control
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Power, GND
RAM Control
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CS_, RD_, WR_, INTR_
CE1_, CE2, OE_, WE_
RAM Addresses
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A16 - A0
ECE-L304 Lecture 7
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RAM Controls
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Subset of NEC RAM (uPD431000A) Control
Table:
Active Low
Logic
WE
L
H
OE
X
L
Mode
WRITE
READ
We also have CS1 and CS2 to deal with
ECE-L304 Lecture 7
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ADC Control
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Get the ADC off-line
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Our acquisition system has only one data
bus, which is shared by the ADC and the
DAC
We have to take the ADC off-line during the
RAM READ cycle so we do not have the
ADC and RAM writing to the bus
simultaneously
ECE-L304 Lecture 7
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ADC Control
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Specify when to get new data
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Take the ADC out of its current freerunning mode
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In free-running mode, the INTR pin signal
initiates a new data conversion when it falls
Synchronize the system
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Generate a new memory address every clock
cycle
Put new data on the bus every clock cycle
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ADC Control
ADC0804 Pins
1
2
3
4
5
6
7
8
9
10
20
CS
19
RD
WR
CLK IN
INTR
DB0
18
17
•
16
•
15
•
•
DB7
CS = Chip Select
RD = Read
WR = Write
INTR = Interrupt
14
13
12
11
ECE-L304 Lecture 7
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ADC Control
Free-Running Circuit
1
2
3
Start
4
5
6
7
8
9
10
CS
RD
WR
CLK IN
INTR
20
19
DB0
18
17
•
16
•
15
•
13
•
DB7
14
CS = Chip Select
RD = Read
WR = Write
INTR = Interrupt
12
11
ECE-L304 Lecture 7
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ADC Control
Free-Running Circuit
1
2
3
Start
4
5
6
7
8
9
10
CS
RD
WR
CLK IN
INTR
20
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19
DB0
18
17
•
16
•
15
•
13
•
DB7
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12
11
While CS is low,
acquisition starts
whenever WR
drops
How can this
happen?
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ECE-L304 Lecture 7
Start switch is
grounded
INTR output falls
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ADC Control
Free-Running Circuit
1
2
3
Start
4
5
6
7
8
9
10
CS
RD
WR
CLK IN
INTR
20 
19
DB0
18
17
•
16
•
15
•
13
•
DB7
14
12
11
ECE-L304 Lecture 7
While CS and RD
are low, data will
appear at the
outputs [DB7:DB0]
as soon as it is
ready
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About 72 internal
clock cycles
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ADC Control
Free-Running Circuit
100 ns min
Rising transition on WR begins the conversion
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ADC Control
Free-Running Circuit
RD must be low for data to appear at
outputs. When RD is high, outputs are Hi-Z.
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ADC Control
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Redesign the connections to the ADC
control pins to get the results you want
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Details of the pin functions are on the data
sheet
Diagrams of control sequences are on the
data sheet
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The first task is to
make sure the 555
clock and the ADC
internal clock are
coordinated.
If WE_ never rises,
no conversions will
occur.
If there are no
conversions, INTR_
will stay high.
There should be no
pulses on WR_ in
READ mode.
When RD_ is high
the ADC output is
high-impedance.
OE_ is low in READ
mode.
Draw a Timing Diagram for the
Control Circuitry
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Which signals are involved
Which ones are inputs and which are outputs
What should the signals look like in order to
get the correct behavior
Try writing the sequence of steps down in
words first, then creating the timing diagram
Keep in mind which signals are active low
and active high, what state does a signal
need to be in during a stage where it is not
switching?
ECE-L304 Lecture 7
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Timing Diagram
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Complete a timing diagram and circuit
schematic for the controls
Have Eric check your results before you
begin construction, and be ready to
answer questions about your decisions
ECE-L304 Lecture 7
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Hints
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Don’t connect power supplies
incorrectly now, if your RAM goes you
will not be happy
Remove your ADC chip during control
signal testing
Check your ADC internal clock - is it fast
enough?
ECE-L304 Lecture 7
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Optimizing the Circuit
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Goal: Record audio to your specs
Storage is limited
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Acquisition speed is limited
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131,072 sites in RAM (217)
ADC internal clock must make about 72 cycles per
conversion
High speed = high bandwidth
High speed = short capture time
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Optimize the Circuit
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You have a design goal for how you
want your circuit to function
If necessary to meet this goal:
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Adjust the ADC internal clock frequency
Adjust the on-board (555) clock
ECE-L304 Lecture 7
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Test the Circuit
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Display analog input (sine or ramp) and
analog output on scope
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During the RAM WRITE cycle, the data on
the bus comes from the ADC
The DAC automatically converts it back to
analog.
At low frequencies, the DAC output should
be identical to the analog input
ECE-L304 Lecture 7
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Test the Circuit
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Display analog input (sine or ramp) and
analog output on scope
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During the RAM READ cycle, the data on
the bus comes from the RAM
The DAC automatically converts it back to
analog
The DAC output should be identical to the
analog input of the previous acquisition
cycle
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Test the Circuit
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Note the length of the acquisition (WRITE)
cycle. Does it equal 131,072 times the period
of the on-board clock?
Note the length of the READ cycle. Does it
equal 131,072 times the period of the onboard clock?
If you want to see if the circuit is really
working, pull the RAM chip
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Your output should be 0 during the READ cycle
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Experimental Results
ECE-L304 Lecture 7
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Deliverables
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Test 1 - Bandwidth
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Analog in, analog out
Determine failure frequency
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A = (Goal - Measured)/Goal
A ≤ 0 (measured exceeds goal) 20 pts
0.95 ≤ A < 1 18 pts
0.90 ≤ A < 0.95 16 pts
A < 0.90 14 pts
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Deliverables
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Test 2 - Address Generator
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Working 17 bits
20 pts
Working 17 bits, novel design 22 pts
Working 16 bits
16 pts
< 16 bits
10 pts
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Deliverables
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Test 3 - RAM/ADC Control
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Working and in sync
Working not in sync
Not working
ECE-L304 Lecture 7
20 pts
15 pts
10 pts
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Deliverables
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Test 4 - Timing
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ADC internal clock period
INTR period
555 timer period
Record time
Playback time
ECE-L304 Lecture 7
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Deliverables
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Test 4 - Timing
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For record time:
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R = (Calculated - Measured)/Calculated
If R ≥ 0.9 10 pts
If R < 0.9 5 pts
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Deliverables
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Test 5 - Playback
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Is DAC output from stored data?
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Yes 20 pts
No 10 pts
ECE-L304 Lecture 7
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Deliverables
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Test 6 - Construction
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Has the circuit been constructed neatly and
with a reasonable floorplan?
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0 to 10 pts
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Deliverables
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Test 7 - Return Board
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Has the circuit been returned in good
condition?
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Good Condition
Damaged
Not Returned
multiplier = 1.0
multiplier = 0.8
multiplier = 0.0
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Deliverables
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Write up your control design:
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Design criteria
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what were the specs you wanted
sketch the desired output waveforms
Sketch the control schematic
Show any equations used, and define
terms if necessary
ECE-L304 Lecture 7
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Deliverables
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Write up your control design:
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Discuss what changes were made to the
circuit to optimize performance
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How effective were they?
Document the performance change
ECE-L304 Lecture 7
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Deliverables
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Have your circuit functionality verified
Comment on your observations and
provide conclusions on the entire
experiment
Any improvements to this Step?
Any improvement to the lab course?
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Yes, we do have class next week
ECE-L304 Lecture 7
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Quiz Next Week
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ADC operation
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DAC
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Sampling rate vs internal clock
Resolution
Resolution
Wire Wrapping
Basic Instrument Operation
Quiz will be in Bossone 303 starting at 6pm
and ending at 6:45pm promptly, no
exceptions
ECE-L304 Lecture 7
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