A Case Study in HW/SW Codesign and RC Project Risk Management: The Honeywell Reconfigurable Space Computer (HRSC)

Jeremy Ramos Advanced Processing Systems Honeywell, Inc.

Clearwater, FL Ian Troxel HCS Research Laboratory University of Florida Gainesville, FL

Presented by: Jeremy Ramos #196 MAPLD 2004

Research Approach

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Honeywell Reconfigurable Space Computer (HRSC) developed to build knowledge base

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Interoperate with current product line

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At least two Virtex class FPGAs for processing

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Support several example applications

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cPCI 6U form factor

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Radiation tolerance/mitigation for path to flight

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Consume less than 40 Watts per board

PMC Slot B PMC Slot A Front Panel cPCI J1,J2 Front Panel cPCI_IF

IO Prototyping Interface IO Prototyping Interface

MemBus

PE1 Virtex 1000

MemBus MemBus Config.

Cache Configuration Manager Configuration, User I/O, and interrupts MemBus DPM 256Kx32

PE2 Virtex 1000

MemBus MemBus

Research Objective

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Data requirements stressing satellite downlinks On-board high-performance computing needed RC has potential to help reduce

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NRE, cycle time, risk, cost

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However, challenges to overcome

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Standard architecture and programming model

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Radiation-hardened components for space

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Power issues

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Project cost and risk models

Prototype, proof-of-concept system needed

Results

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HRSC built under budget and on time

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One year from concept to running applications

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At most 5 FTE engineering effort at any time

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Board worked on first boot with 2 jumper wires

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Many factors contributed to project success

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HW/SW codesign

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Simulation/Emulation/Hardware environments

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Spiral development process

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Reduction in Non-Recurring Engineering

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Streamlined design and documentation process