Transcript No Slide Title

Handling Asynchronous Inputs
ECEn 224
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© 2003-2008
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Asynchronous Signals
• Definition: A signal that can change at any
time with respect to the clock.
• Examples:
– Push buttons
– Keystrokes
– Digital signals from different clock domain
ECEn 224
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Two Problems with Asynchronous Inputs
1. Flip flops could become metastable
2. State machines may transition to incorrect
next state
These are two independent problems.
ECEn 224
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Problem #1
Metastability
ECEn 224
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Asynchronous Signals
• Problem: Asynchronous signals do not always
respect setup and hold times
– Asynchronous signals may change at any time
ok
ok
bad bad
ok
ok
tsetup
thold
Clock
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Metastability
• Imagine if R is pulsed high for a very short time then
goes back low…
– Could it impart just enough energy to get Q halfway
between ‘1’ and ‘0’?
– Latch might hang at the midway point for some time
• Could be a short time, could be a long time
– This is called metastability
R=0
Q=1
Q’=0
S=0
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Metastability
• Violating tsetup for a D flip flop can cause very
short pulses on signals Y and Z, and make flip
flop metastable
D
Y
Q
Q’
Z
CLK
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Metastability
• Once a flip flop goes metastable, it is
impossible to bound how long it will remain
there
Analogy: Roll ball up roof just hard
enough to get it to balance on top…
ECEn 224
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Metastability
• Once a flip flop goes metastable, it is
impossible to bound how long it will remain
there
Analogy: Roll ball up roof just hard
enough to get it to balance on top…
When will it come down?
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Probability of Metastability
• The probability of an asynchronous signal causing metastability
in a given clock cycle is very low
• However, there are millions or even billions of clock cycles every
second
• Mean Time Between Failure (MTBF) quantifies how often a flip
flop with an asynchronous input is likely to go metastable
• MTBF depends on:
– Flip flop’s clock frequency
– Frequency of changes on the asynchronous input
– Electrical characteristics of the flop flop
• Typical MTBF numbers can range from minutes for high
frequency systems to thousands of years for slower devices
ECEn 224
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Metastability Solutions
• Solution #1: Specially-designed flip flops that
are particularly resistant (hardened )
• Solution #2: Multiple FF’s in series increases
resistance to metastability
– At the expense of response time
AsynchronousIn
D Q
D Q
SynchronizedOut
Could also be hardened flip flops
ECEn 224
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Problem #2
May Lead to Wrong Next State
(No metastability involved here…)
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Wrong Next State
• Asynchronous inputs might cause the wrong
next state to be loaded
• Two possible causes:
– Unequal logic path lengths (Cause A)
– False outputs on IFL outputs (Cause B)
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Cause A: Unequal Path Lengths
A’
IFL
N1
00
A
D Q
C1
5ns
A
clk
N0
10ns
11
D Q
C0
clk
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Cause A: Unequal Path Lengths
A’
IFL
N1=0
00
A
D Q
Q1=0
5ns
clk
A=0
N0=0
10ns
11
D Q
Q0=0
clk
Time t = 12 ns
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Cause A: Unequal Path Lengths
A’
IFL
N1=0
00
A
D Q
Q1=0
5ns
clk
A1
N0=0
10ns
11
D Q
Q0=0
clk
Time t = 13 ns
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Cause A: Unequal Path Lengths
A’
IFL
N11
00
A
D Q
Q1=0
5ns
clk
A1
N0=0
10ns
11
D Q
Q0=0
clk
Time t = 18 ns
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Cause A: Unequal Path Lengths
A’
IFL
N11
00
A
D Q
Q11
5ns
clk
A1
N0=0
10ns
11
D Q
Q0=0
clk
Time t = 20 ns (clock rises)
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Erroneous State Transition
CLK
A’
A
N1
00
N0
A
11
Current
State
00
0
5
10
10
5ns
25
30
Wrong next state!!
10ns
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Erroneous State Transition
CLK
A’
Danger
period
A
N1
00
N0
A
11
Current
State
00
0
5
10
10
5ns
25
30
10ns
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Solution #1: Synchronize Signal A
IFL now sees
synchronous
input
IFL
N1
D Q
C1
5ns
A
clk
D Q
N0
clk
10ns
Synchronizing flip flop is still susceptible to
metastability due to setup time violations.
D Q
C0
clk
But that is a different problem with previously-seen solutions.
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Solution #2: Use Gray Codes for States
Will never have case
when both paths
transitioning…
A’
00
A
A’
IFL
N1
01
A
C1
5ns
A
clk
N0
11
D Q
10ns
11
State change will occur or it won’t…
ECEn 224
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C0
clk
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Cause B: False Outputs
• Gray coding state transitions doesn’t always
work!
• We can still have false outputs on our input
forming logic
• These hazards can also lead to incorrect
transitions
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Logic Hazards
A
Asynchronous input A
BC
A’
B
F
A
C
0
1
00
0
0
01
0
1
11
1
1
10
1
0
F = A’B + AC
This is the conventional K-map solution
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Gates Have Real Timing…
A
A’
B=1
A
C=1
g1
g1
F
g2
g2
F
Called a false output
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Gates Have Real Timing…
A
A’
B=1
A
C=1
g1
g1
F
g2
g2
F
If the clock edge occurs here… you’re toast!
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Hazard-Free Logic Design
• Make sure all adjacent 1’s are covered by the
same prime implicant
– Add redundant prime implicants as needed
A
BC
0
1
00
0
0
01
0
1
11
1
1
10
1
0
A’
B
A
C
Redundant but
will eliminate
false output
B
C
g1
g2
F
g3
On ABC = ‘111’ to ABC = ‘011’,
g3 will hold F high entire time.
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No False Output…
A’
B=1
g1
g2
A
C=1
B=1
C=1
g3
A
BC
F
A
g1
g2
0
1
00
0
0
01
0
1
11
1
1
10
1
0
g3
F
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Solution #3
• Use both gray code states and hazard-free logic minimization
– Gray code encoding ensure only one state bit changes
• Solves the unequal path problem
– HFLM ensures no hazards (false outputs) exist on input
forming logic
IFL
S’
N1
01
D Q
C1
5ns
A
clk
S
N0
11
10ns
D Q
C0
clk
ECEn 224
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© 2003-2008
BYU
Asynchronous Input Problem Summary
• Problem #1: Asynchronous inputs can cause
flip flops to enter a metastable state
• Problem #2: Asynchronous inputs can cause
invalid state transitions
A) Different propagation delays on IFL paths to
different state bits
B) False outputs on IFL outputs
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Solutions Summary
•
Metastability
– Solution #1: Use hardened flip flops
• May not be available
– Solution #2: Add flip flops in series to decrease susceptibility
• Latency may cause problems, if we need to react immediately
•
Invalid State Transitions
– Solution #1: Synchronize asynchronous inputs with a flip flop
• Simplest solution
• Latency may cause problems, if we need to react immediately
– Solution #2: gray code state encoding (doesn’t always work)
– Solution #3: gray code + hazard-free IFL
•
•
•
•
•
Takes extra hardware
May require additional states to get gray code transitions
Use when need to react quickly to input
FF’s still susceptible to metastability
HFLM only works for single-input changes
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The same
solution!
© 2003-2008
BYU
Other Asynchronous Input Issues
ECEn 224
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© 2003-2008
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Multiple Asynchronous Inputs
• What if we have a state transition that
depends on multiple asynchronous inputs?
A’•B’
S0
A’•B
S2
A
S1
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Multiple Asynchronous Inputs
• Break up the states so that only one
transition is dependant on each input
A’•B’
S0
A’•B
S0
B’
A’
A
A
S2
B
S2
S1
S1
S3
ECEn 224
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Multiple Clock Systems
• When you make up the rules
– You can cheat…
• In this class we cheat:
– One global clock

simplifies our work
• In the real world:
– Systems have multiple clocks
ECEn 224
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Multi-clock System
•
This is a PCI Express board that plugs into a computer’s motherboard
RAM (DDR SDRAM)
FPGA
Video DAC
PCI-E Interface (PHY)
PCI-E Connector
ECEn 224
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Multi-clock System
•
This is a PCI Express board that plugs into a computer’s motherboard
200 MHz
100 MHz
25.175 MHz
How do they talk
to each other?
250 MHz
2.5 GHz
ECEn 224
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Multi-Clock Systems
• This system has multiple clock domains
• Signals that cross domains look like
asynchronous signals to the other domain
• For simple control signals, we can use one of
the methods discussed in this lecture
– Synchronizing flip flops
– Hazard free logic + gray codes
• When data transfer is involved, the required
solutions are more complicated (ECEn 320)
ECEn 224
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© 2003-2008
BYU