ECE 477 Final Presentation Group ?? Fall 2004

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Transcript ECE 477 Final Presentation Group ?? Fall 2004

ECE 477 Design Review Team 4

Spring 2006

Justin Thacker, Matt Kocsis, Ian Snyder, Dustin Poe

Outline

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Project overview Project-specific success criteria Block diagram Component selection rationale Packaging design Schematic and theory of operation PCB layout Software design/development status Project completion timeline Questions / discussion

Project Overview

The Digital Real-time Intelligent Networked Kegerator will address safety, legal, usability, and economic concerns of draft beverage distribution. Alcohol consumption monitoring will provide a tool to allow a person to know exactly how much they have consumed, learn estimated legal limits, and reduce unauthorized or unlawful drinking. System control and monitoring will allow users to track inventory, decrease beverage waste, and predict future resource needs.

Project-Specific Success Criteria

• • • • •

An ability to sense and control beverage temperature. An ability to identify authorized users via electronic identification. An ability to track consumption on an individual basis.

An ability to display user/device status on an LCD.

An ability to control the function of and report the status of the kegerator via an embedded web server.

Block Diagram

$1-$20 Bill Acceptor Web Interface Expansion PLD Graphical LCD Screen RS-232 Optical Encoder w/Pushbutton Quadrature Input Human-Machine Interface RCM3315 Microcontroller Module Temperature Probes Flowmeters Solenoids Compressor Contactor Control and Monitoring RFID Module User Authentication Biometric Identification Module

Microprocessor Selection

Device Model Module Manufacturer Packaging SRAM Flash Extended Memory General-Purpose I/O Serial Interfaces Real-Time Clock SRAM Battery Backup Timers Pulse-Width Modulators Analog to Digital Quadrature Decoder Ethernet Power Cost RCM3315 Rabbit Semiconductor Core Module Board 512K Program + 512K data 512K 4 Mbyte Serial Flash (single chip) 49 5 total with 5 configurable as SCI, 3 as SPI Yes Yes Ten 8-bit and one 10-bit 10-bit free-running counter and 4 PWM regs No Yes 10/100 3.15-3.45V DC, 275 mA @ 3.3V

$99 CM-HCS12NE64 Softec Microsystems Core Module Board HCS12NE64 N/A 112-Pin LQFP 8K 64K No No 8K 64K 8 Mbyte Serial Flash (1 Mbyte x 8) None Up to 70 2 SCI, 1 SPI, 1 I 2 C Up to 70 2 SCI, 1 SPI, 1 I 2 C No No Ten 8-bit and four 16-bit None Yes No Ten 8-bit and four 16-bit None Yes No 10/100 3.3V

10/100 3.3V

$600 @ $120 each (Minimum Qty 5) 8 (+$25 for components)

LCD Selection

Device Model Module Manufacturer Screen Manufacturer Screen Technology Evaluation Board Samples Available Cost ezLCD-001 ezLCD Sony Active Matrix TFT Color Resolution (pixels) Diagonal Size Viewable Area (cm 2 ) Contrast Ratio Yes 240x160 2.7" 37.03

13 to 1 Response Time (ms) Controller 15 ezLCD-001 Controller Flash Interface 94k Serial, USB, I High level control functions Yes 2 C, Parallel Yes Yes $200 ($150 for students) F-51851GNFQJ-LY-AND Apollo Displays Optrex STN Transmissive No 240x64 5.7" 48.96

6 to 1 310 CDS-51405 None Serial, Parallel Yes No Cannot get controller $171 CFAG320240C-FMI-T Crystalfontz Crystalfontz STN Transmissive No 320x240 5.7" 110.4

3 to 1 350 S1D3305 None Parallel No No Yes $142.73

RFID Reader Selection

Device Model Module Manufacturer Module Package Frequency Antenna Replaceable Antenna Interface Board Cables Cost RI-K3A-001A Low Frequency Micro RFID Kit Phidget USB RFID Kit Texas Instruments 32 pin DIP 134.2 kHz 80mm Disk Yes Typical Read Range (cm) 15 Transponder Samples Software Yes Yes Yes $284 Phidget USA PCB 125 kHz 63mm Onboard Coil No 4 cm Yes No Yes $76.95

RX-MFR-RNLK

Texas Instruments PCB 134.2 kHz/13.56 Mhz LF/HF Antennas Yes RS-232, RS-485 10+ cm Yes Yes Yes $625 ($350 for students)

Packaging Design

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Self contained unit Easy to add on to existing system

Schematic/Theory of Operation

Schematic/Theory of Operation

Schematic/Theory of Operation

Schematic/Theory of Operation

Schematic/Theory of Operation

Schematic/Theory of Operation

Schematic/Theory of Operation

Schematic/Theory of Operation

PCB Layout

236 mm 117 mm

Bottom Copper

Digital Gnd i Analog Gnd / Power Gnd 50 mil Pins 2 and 3 Internally Connected Single Point of Analog and Digital Ground

Top Copper

5V Traces 50 mil 3.3V

12V 50 mil 12V 60 mil

PCB Layout

Serial Interface Biometric Future Dev RCM3315 Microcontroller Module 5V and 3.3V Converters Temp/ Compress Common Beverage Interface

Common Beverage Interface

•Have common I/0 simplified easily through symmetry •Segregates High Current Analog From Rest of Circuit

DC to DC Converter

Traces made short and large as possible

Bypass Capacitors mounted underneath to get as close as possible

Power and Signal Gnds Segregated

EMI reduction

Software Design/Development Status • • •

All functions built into costate statements.

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Temperature polling Rabbit web External events triggered by interupts.

Flowmeters: code working on rabbit Other hardware over serial communication.

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Bill Validator: code working on rabbit RFID: code working on rabbit LCD: code working on computer

Project Completion Timeline

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Week 8 – PCB and Schematic finalization and test circuits Week 9 – Finalize PCB and test circuits Week 10 – Complete all functional software modules and hardware testing Week 11 – PCB integration and testing Week 12 – Integrate controller functions with web and hardware testing Week 13 – Add complex features Week 14 – Test complex features, create video and poster Week 15 – Final Presentation, Report

Questions / Discussion