Transcript Graphical User Interface for Reconfigurable Processor

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Graphical Design Environment for a
Reconfigurable Processor
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David M. Buehler
Institute of Advanced Microelectronics
ECE/CAMBR
University of Idaho
[email protected]
Institute of Advanced Microelectronics
ECE/CAMBR
University of Idaho
[email protected]
Gregory Donohoe
Pen-Shu Yeh
Institute of Advanced Microelectronics
ECE/CAMBR
University of Idaho
[email protected]
NASA GSFC
Code 567
[email protected]
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Overview
Field Programmable Processor Array (FPPA)
Graphical Programming
FPPA Matlab Simulink model (floating point)
FPPA graphical interface design flow
Examples
Summary
Future work
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Field Programmable Processor
Array (FPPA)
• An embedded data processor VLSI chip for spacecraft.
– Radiation-tolerant, 0.25m CMOS process
– 16 on-board, fixed point processing elements
– Implements a reconfigurable synchronous data flow processor
• Run-time reconfigurable
• Extensible by tiling multiple chips
– Serves as accelerator to a host CPU
• Application development:
• Text base development
– Configuration and Run-time compilers
– Standalone functional simulator
• FPPA Simulink graphical design environment (GUI)
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FPPA Data Path Elements
FPPA features:
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PE00
PE03
IOM0
BSEL0
PE11
PE10
LBUS0
16 configurable on-board PEs
• Four 16-bit-wide, bidirectional I/O ports
PE01
LBUS1
PE02
PE13
BSEL1
PE12
• One 16-bit-wide dedicated output port
IOM1
• On-board program memory and execution unit
DOM
XBAR
IOM2
• Interface control signals
BSEL2
BSEL3
IOM3
PE30
PE31
PE24
LBUS3
PE33
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PE21
LBUS2
PE32
PE23
PE22
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Processing Element (PE) components
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Inputs
Delay Elements
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16
mul_Y
alu_X
alu_Y
Y
mul_X
ALU
ALU_OUT
MUL_OUT
Format
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X
16
16
Format
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Conditional Output
Select
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16
Secondary
Output
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Primary
Output
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Control
Output
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Example of the simple pipeline using multiple PEs
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FPPA programming complexity
Data path descriptions
1. PE
2. Cluster
3. I/O
PE00
PE03
BSEL0
PE1
1
PE10
LBUS0
IOM
0
• Runtime descriptions
• Enable / Disable PEs
• External peripherals
PE01
LBUS1
PE02
PE13
BSEL1
PE12
IOM1
DOM
XBAR
IOM2
IOM3
BSEL3
PE30
PE31
PE24
LBUS3
• Procedural languages like C do
not naturally describe a dataflow
architecture like the FPPA
PE33
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BSEL
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PE21
LBUS2
PE32
PE23
PE22
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Realizing 4 taps FIR filter with FPPA
Data Path:
Difference Equation:
Routing of input data:
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Routing of output and local bus data:
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Graphical Programming
• Naturally represents dataflow computational
model
• Quick to learn
• Familiar Matlab Simulink graphical design
environment
• Floating point versus Fixed point implementation
• Rapid Development and Validation
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FPPA Simulink Model
• Data path
PE00
– Computational PE
– Conditional PE
• Runtime
– Enable / Disable PEs
and modules
PE10
PE01
LBUS0
IOM0
PE03
BSEL0
PE11
LBUS1
PE13
PE02
BSEL1
PE12
IOM1
DOM
XBAR
• Data format
IOM2
IOM3
PE30
BSEL3
PE31
PE24
LBUS3
PE33
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PE21
LBUS2
PE32
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BSEL2
PE23
PE22
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General Model of the Processing Element
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Processing Element (PE)
Input
X
1/Z
Y
1/Z
W
1/Z
Function (X, Y, W, C0, C1, DP, RT) => output
Output
Configuration
Constants
(C0, C1)
Data Path
(DP)
Run Time
(RT)
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Simulink PE model (Data path)
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Simulink PE model (Data path)
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1.
2.
Unconditional PE
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Delay
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Shift right or left
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(X + Y)
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(X – Y)
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(X + Y) * Z
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(X - Y) * Z
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(X*Y – Z)
•
(X*Y + Z)
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C0, C1
Conditional PE
If (condition) then
Perform task A
Else
Perform task B
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Simulink PE model (Run Time)
• Fire pattern
– Example:
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Fire pattern = [1] “PE always enable”
Fire pattern = [1 0] “PE enable every other instruction”
Fire pattern = [1 0 0 0] “PE enable every 4th instruction”
…
– Potential applications
• Multi-rate Signal Processing
• Multi-functionality in one FPPA
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FFPA graphical interface design flow
Note:
SIFOpt tool is a result of
David M. Buehler dissertation
at the University of Idaho.
Simulink
Algorithm
Model (floating point)
• Design Data Path
• Provide Input data
• Data format
• Run time
result
Golden
model
Validation
result
PERL
(floating  fixed point)
Data Path
Data format
Run Time
SIFOpt
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FPPA C++ simulator
(fixed point model)
ConfigASM
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Example # 1: Realizing 4 tap FIR filter
Difference Equation
Input waveform
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Output waveform
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Example # 2: Wavelet
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(Multi-rate filter bank)
Source
L1
Low Pass
L
L2
Low Pass
Decimate by 2
L
L3
Low Pass
L
Decimate by 2
L4
Low Pass
Decimate by 2
L
Decimate by 2
Low Pass filter:
• 4 taps with Debenchies coefficients
• Debenchies coefficients are normalized by sqrt(2) to get the sum equal to one
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Example # 2: Model 4 series filters
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Example # 2: Model Down Sampling
Run Time: Down Sampling
1
01
0001
00000001
0000000000000001
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Example 2: FPPA view
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Example #2: Simulation result
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Future work
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• Data path optimization
– Speed
– Area
• Cook book for common use circuits
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Square root
Division
Trigonometry functions
Iterative methods
Down / Up sample
Matrix computation
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Summary
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• Present FPPA
• FPPA programming complexity
• Graphical programming environment
– Intuitive
– Fast and easy
• Validation and Verification
– Matlab => Floating point
– FPPAsim => hardware specific
• Compile to FPPA code
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