Transcript Slide 1
SMCS332SpW / SMCS116SpW SpaceWire compliant Communication Controller ASICs Stephan Fischer, Lars Stopfkuchen, Uwe Liebstückel, Paul Rastetter, Luca Tunesi2 EADS Astrium GmbH Munich, 2ESA / ESTEC Applications: Motivation for Upgrading SMCS332 and SMCS116: Existing SMCS332 and SMCS116 are often used, but not compliant to Typical Environment : SMCS332SpW and SMCS116SpW within a point-to- SpaceWire standard (ECSS-E-50-12A) point SpaceWire network Anomalies shall be corrected Sensor 1 Need for protocol due to upcoming SpaceWire Networks with Routers Sensor 2 FIFO I/F Memory 1 ADC I/F RAM I/F SMCS116SpW SMCS116SpW Advantages due to SpaceWire: Resistance against simultaneous switching on the data and strobe inputs HOCI SMCS332SpW SMCS116SpW SpaceWire Point-to-Point Links Time distribution possible HOCI SMCS332SpW ‘Hot’ pluggable, i.e. no Master-Slave situation has to be arranged Processor simple interface (approx. 5000 Gates) high-speed (a few to hundreds of MBit/s) SMCS116SpW SMCS116SpW SMCS116SpW FIFO I/F FIFO I/F RAM I/F Telemetry Telecommand Telemetry Telecommand Memory 2 Features of SMCS116SpW: Features of SMCS332SpW: 3 SpaceWire links allowing full duplex communication with selectable bitrate 1 SpaceWire link from 1.25 up to 200 MBit/s (100 MBit/s with 3 V supply) from 1.25 up to 200 MBit/s (100 MBit/s with 3 V supply) supports Serial Transfer Universal Protocol (STUP) Communication Memory Interface (COMI) provides autonomous access to a Host Interface to program and control the SMCS116SpW communication memory. FIFO Interface configurable between 8 and 16 bit mode Processor SMCS332SpW 8/16/32-Bit Little or Big Endian mode HOSTBIGE BOOTLINK RESET CLK CLK10 is configurable Host Control Interface gives read/write access to the 4 SpW-Link 1 4 SpW-Link 2 4 SpW-Link 3 4 HINTR HSEL HRD HWR HACK HDATA HADR SMCSADR SMCSID 32 8 4 4 CMCS0 CMCS1 CMRD CMWR CMDATA CMADR CPUR SES 32 16 configuration registers Control-by-Link Wormhole routing allows hardware RAM RAM 2 SELECT_A OE_A SELECT_A WE_A OE_A DATA_A WE_A ADDR_A DATA_A ADDR_A CAM COCO COCI JTAG DAC Interface ID 5V/3,3V 5 ADC Interface allows to connect an ADC with a width of up to 16 bits INTERRUPT_IN CHIP_SELECTS READ WRITE WAIT/ACK DATA ADDRESS RAM Interface provides a 8/16-bit SELECT_B OE_B SELECT_B WE_B OE_B DATA_B WE_B ADDR_B DATA_B UART1 data bus and a 16-bit address bus ADDR_B 2 UART Interfaces DATA[15:0] SMCS116SpW up to 24 GPIO SMCS332SpW as communication interface for a processor RAM RAM 16 5 SpaceWire Dual Port Communication Dual Port Memory Communication Memory 16 ADDR[15:0] CTRL BUS Two 32-bit on-chip timer routing of packets Enhanced 32-bit processor support New header field control bit that gives more flexibility for packet generation SEU FREE GPIO HOCI 8 11 RAM RAM 6 RAM RAM 4 x (64K x16) Arbitrary packet length SMCS116SpW as communication controller for a memory No packet size restriction for data over COMI SEU FREE Implementation of SMCS332SpW Serial Transfer Universal Protocol (STUP): SEU free cell library (0,5 µm) from implemented in SMCS116SpW CADR Receive COMI minimized complexity ATMEL makes it possible to use SMCS116SpW within a SpaceWire Network with 196 pins ceramic quad flat pack SpaceWire SpW Macro Cell Protocol CDATA HADR Transmit HCTRL HOCI (MQFP) distinct protocols CCTRL HDATA HINT SpaceWire Channel 2 first byte transmitted Destination Path Address Power Consumption: 1,7 W (max) Destination Path Address Destination Path Address RCPU PRCI SpaceWire Channel 3 JTAG Destination Logical Address Protocol Identifier Source Logical Address (Return Address) Checksum Checksum End of packet marker (EOP) SES TEST Data (one or more bytes) GPIO last byte transmitted Implementation of SMCS116SpW UARTs SEU free cell library (0,5 µm) from SpaceWire leading path addresses are stripped off on the way through the network Link-IF Protocol Identifier follows the logical address, unknown protocol ID’s are Controller 12 Checksum over data bytes is optional MAPLD 2005/182 -- Stopfkuchen ATMEL 100 pins ceramic quad flat pack HOST-IF for SMCS116SpW: first data byte is interpreted as command (read/write) in conjunction with 7- Bit SMCS116SpW register address 28 FIFO-IF RAM-IF Data Bus ignored ADC-IF Control Bus DAC-IF 16 (MQFP) Power Consumption: 0,7 W (max) Timer