Transcript Slide 1
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Microprocessor Control of Manufacturing Systems and Introduction to Mechatronics
Instructor: Professor Charles Ume Analog to Digital Converter George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Presentation Outline
• Introduction: Analog vs. Digital?
• Examples of ADC Applications • Types of A/D Converters • A/D Subsystem used in the microcontroller chip • Examples of Analog to Digital Signal Conversion • Successive Approximation ADC George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Analog Signals
Analog signals – directly measurable quantities in terms of some other quantity Examples: • Thermometer – mercury height rises as temperature rises • Car Speedometer – Needle moves farther right as you accelerate • Stereo – Volume increases as you turn the knob.
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Digital Signals
Digital Signals – have only two states. For digital computers, we refer to binary states, 0 and 1. “1” can be on, “0” can be off.
Examples: • Light switch can be either on or off • Door to a room is either open or closed George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Examples of A/D Applications
• Microphones electrical signals convert pressure waves in the air into varying • Strain Gages resistance changes with applied strain • Thermocouple energy to electric energy temperature measuring device converts thermal • Voltmeters • Digital Multimeters George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Just what does an A/D converter DO?
• Converts analog signals into binary words George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Analog
Digital Conversion 2-Step Process:
• Quantizing - breaking down analog value is a set of finite states • Encoding - assigning a digital word or number to each state and matching it to the input signal George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Step 1: Quantizing
Output States Example: 0 You have 0-10V signals. Separate them into a set of discrete states with 1.25V increments. (How did we get 1.25V? See next slide…) 1 2 3 4 5 6 7 Discrete Voltage Ranges (V) 0.00-1.25
1.25-2.50
2.50-3.75
3.75-5.00
5.00-6.25
6.25-7.50
7.50-8.75
8.75-10.0
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Quantizing
The number of possible states that the converter can output is:
N=2 n where n is the number of bits in the AD converter Example: For a 3 bit A/D converter, N=2 3 =8.
Analog quantization size:
Q=(V max -V min )/N = (10V – 0V)/8 = 1.25V
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Encoding
• Here we assign the digital value (binary number) to each state for the computer to read.
Output States 0 1 2 3 4 5 6 7 Output Binary Equivalent 000 001 010 011 100 101 110 111 George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Accuracy of A/D Conversion
There are two ways to best improve accuracy of A/D conversion: • increasing the resolution which improves the accuracy in measuring the amplitude of the analog signal.
• increasing the sampling rate which increases the maximum frequency that can be measured.
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Resolution
• Resolution (number of discrete values the converter can produce) = Analog Quantization size (Q) (Q) = V range / 2 n , where V range which can be represented is the range of analog voltages • limited by signal-to-noise ratio (should be around 6dB) • In our previous example: Q = 1.25V, if we used a 2-bit converter, then the resolution would be 10/2^2 = 2.50V.
George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Sampling Rate
Frequency at which ADC evaluates analog signal. As we see in the second picture, evaluating the signal more often more accurately depicts the ADC signal. George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Aliasing
• Occurs when the input signal is changing much faster than the sample rate. For example, a 2 kHz sine wave being sampled at 1.5 kHz would be reconstructed as a 500 Hz (the aliased signal) sine wave. Nyquist Rule: • Use a sampling frequency at least twice as high as the maximum frequency in the signal to avoid aliasing.
George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Overall Better Accuracy
• Increasing both the sampling rate and the resolution you can obtain better accuracy in your AD signals.
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A/D Converter Types
• Converters – Flash ADC – Delta-Sigma ADC – Dual Slope (integrating) ADC – Successive Approximation ADC George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Flash ADC
• Consists of a series of comparators, each one comparing the input signal to a unique reference voltage.
• The comparator outputs connect to the inputs of a priority encoder circuit, which produces a binary output George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Flash ADC Circuit
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How Flash Works
• As the analog input voltage exceeds the reference voltage at each comparator, the comparator outputs will sequentially saturate to a high state. • The priority encoder generates a binary number based on the highest-order active input, ignoring all other active inputs.
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ADC Output
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Flash
Advantages • Simplest in terms of operational theory Disadvantages • Lower resolution • Most efficient in terms of speed, very fast • limited only in terms of comparator and gate propagation delays • Expensive • For each additional output bit, the number of comparators is doubled • i.e. for 8 bits, 256 comparators needed George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Sigma Delta ADC
• Over sampled input signal goes to the integrator • Output of integration is compared to GND • Iterates to produce a serial bit stream • Output is serial bit stream with # of 1’s proportional to V in George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Outputs of Delta Sigma
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Sigma-Delta
Advantages • High resolution • No precision external components needed Disadvantages • Slow due to oversampling George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Dual Slope Converter
V in t FIX t meas t • The sampled signal charges a capacitor for a fixed amount of time • By integrating over time, noise integrates out of the conversion • Then the ADC discharges the capacitor at a fixed rate with the counter counts the ADC’s output bits. A longer discharge time results in a higher count George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Dual Slope Converter
Advantages • Input signal is averaged • Greater noise immunity than other ADC types • High accuracy • Slow Disadvantages • High precision external components required to achieve accuracy George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Successive Approximation ADC
• A Successive Approximation Register (SAR) is added to the circuit • Instead of counting up in binary sequence, this register counts by trying all values of bits starting with the MSB and finishing at the LSB.
• The register monitors the comparators output to see if the binary count is greater or less than the analog signal input and adjusts the bits accordingly George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Successive Approximation ADC Circuit
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Output
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Successive Approximation
Advantages Disadvantages • Capable of high speed and reliable • Medium accuracy compared to other ADC types • Good tradeoff between speed and cost • Higher resolution successive approximation ADC’s will be slower • Speed limited to ~5Msps • Capable of outputting the binary number in serial (one bit at a time) format.
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ADC Types Comparison
Dual Slope Flash Successive Approx Sigma-Delta ADC Resolution Comparison
Type
Dual Slope Flash Successive Appox Sigma-Delta 0 5 10 15 Resolution (Bits)
Speed (relative)
Slow Very Fast Medium – Fast Slow Med High Low Low 20
Cost (relative)
25 George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Successive Approximation Example
• 10 bit resolution or 0.0009765625V of Vref • Vin= .6 volts • Vref=1volts • Find the digital value of Vin George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Successive Approximation
• MSB (bit 9) – Divided V ref by 2 – Compare V ref /2 with V in – If V in – If V in is greater than V – V in =0.6V and V=0.5
ref /2 , turn MSB on (1) is less than V ref /2 , turn MSB off (0) – Since V in >V, MSB = 1 (on) George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Successive Approximation
• Next Calculate MSB-1 (bit 8) – Compare V in =0.6 V to V=V ref /2 + V ref /4= 0.5+0.25 =0.75V
– Since 0.6<0.75, MSB is turned off • Calculate MSB-2 (bit 7) – Go back to the last voltage that caused it to be turned on (Bit 9) and add it to V ref /8, and compare with V in – Compare V in with (0.5+V ref /8)=0.625
– Since 0.6<0.625, MSB is turned off George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Successive Approximation
• Calculate the state of MSB-3 (bit 6) – Go to the last bit that caused it to be turned on (In this case MSB-1) and add it to V ref /16, and compare it to V in – Compare V in to V= 0.5 + V ref /16= 0.5625
– Since 0.6>0.5625, MSB-3=1 (turned on) George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Successive Approximation
• This process continues for all the remaining bits. George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Using the Analog to Digital Converter in the MC9S12C32
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ME4447/6405 • Interfaces to external signals via Port AD • 10- or 8-bit Successive Approximation ADC George W. Woodruff School of Mechanical Engineering, Georgia Tech
ME4447/6405 • 8 input channels • Subsystem operation controlled by ADCTL2-5 Registers • Results placed in ATDDR0-7 George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Conversion Sequence
• Power on • Wait 20 μs for ATD power to stabilize • Sample • Successive Approximation • End • Conversion time – 8-bit: 12-26 ATD Clock Cycles – 10-bit: 14-28 ATD Clock Cycles George W. Woodruff School of Mechanical Engineering, Georgia Tech
ME4447/6405 Output States 0 1 2 … 255 Discretized Voltage Range 0 - 19.5 mV 19.6 - 39.0 mV 39.1 - 58.5 mV … 4.98 - 5.0 V Binary Coded Equivalent $00 $01 $02 … $FF • MC9S12 8 bits • Voltage Range = (V RH 2 8 = 256 • MC9S12 accepts 0 – 5V range – V RL )/255 * State George W. Woodruff School of Mechanical Engineering, Georgia Tech
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ATDCTL2 $0082
• • • • • • • • ADPU: ATD ON (1) or OFF (0) AFFC: ATD Flag clears automatically (1) or Must read status register to clear flag (0) AWAI: ATD off in wait mode (1) or on in wait mode (0) ETRIGLE: External trigger on edge (0) or level (1) ETRIGP: Controls polarity of ext. trigger Falling edge/low level (0) or rising edge/high level (1) ETRIGE: Enables (1) or disables (0) external trigger ASCIE: ATD Sequence Complete Interrupt Enable Bit - Enabled (1) or Disabled (0) ASCIF: ATD Sequence Complete Interrupt Flag - No ATD interrupt occurred George W. Woodruff School of Mechanical Engineering, Georgia Tech
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ATDCTL3 $0083
• • • S8C,S4C,S2C,S1C: Set the number of Conversions per sequence FIFO: Conversion results are mapped to corresponding result registers (0) or result registers are used as a rotating First In First Out (FIFO) queue (1) FRZ1,FRZ0: Determine function of ATD system during Freeze mode George W. Woodruff School of Mechanical Engineering, Georgia Tech
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ATDCTL4 $0084
• • • SRES8: 8-bit (1) or 10-bit (0) resolution SMP1,SMP0: Determines length of second part of sample PRS4:0: ATD clock prescaler bits George W. Woodruff School of Mechanical Engineering, Georgia Tech
ME4447/6405 • Prescaler determines ATD Clock frequency • Derived from Bus Clock Frequency George W. Woodruff School of Mechanical Engineering, Georgia Tech
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ATDCTL5 $0085
• • • • • DJM: Left Justified (0) or Right Justified (1) data in result registers DSGN: Unsigned data in result registers (0) or signed data in result registers (left justification only) (1) SCAN: Single conversion (0) or continuous conversion sequence (1) MULT: Sample only one channel (0) or sample across multiple channels (1) CC,CB,CA: Determine the channel to be sampled if MULT=0 or the first channel to be sampled if MULT = 1 George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Left Justified Data
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Right Justified Data
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ATDSTAT0 $0086
• • • • SCF: Conversion Sequence not completed (0) or completed (1) ETORF: External Trigger Overrun Flag - No overrun has occurred (0) or overrun has occurred (1) FIFOR: FIFO Overrun Flag - No overrun has occurred (0) or overrun has occurred (1) CC2:0: Determine the result register that will contain the current conversion George W. Woodruff School of Mechanical Engineering, Georgia Tech
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ATDSTAT1 $008B
• CCFX: Conversion number X has not yet completed (0) or has completed and the result is available in ATDDRX (1) George W. Woodruff School of Mechanical Engineering, Georgia Tech
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ATDDIEN $008D
• IENX: Disable digital input on PTADX (0) or enable digital input on PTADX George W. Woodruff School of Mechanical Engineering, Georgia Tech
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PORTAD $008F
• PTADX: Contains digital input value for port AD pin X George W. Woodruff School of Mechanical Engineering, Georgia Tech
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Example
• Write a program to configure the ATD system to perform one capture of an analog signal from Channel 0 with an 8-bit resolution George W. Woodruff School of Mechanical Engineering, Georgia Tech
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ATDCTL2 ATDCTL4 EQU EQU ATDCTL5 ATDDR1H EQU EQU ATDSTAT1 EQU $0082 $0084 $0085 $0092 $008B ORG ADRESULT RMB ORG LDAA STAA LDAA STAA DELAY LDY DEY BNE LDAA STAA $2000 1 $1000 #$80 ATDCTL2 #$85 ATDCTL4 #160
Power on ATD Subsystem
;ADPU=1
8-bit resolution, appropriate prescaler
;SRES8=1, PRESCALER BITS = 00101 ;delay for 20
m
s
Delay for power to stabilize
DELAY #$01 ;SCAN=0,MULT=0,CC:CA=001 ATDCTL5 ;start conversion
Set ADCTL to start conversion
LDX BRCLR 0,X #$02 LDAA #ATDSTAT1 ;check for complete flag ;CCF1 is bit 1 ATDDDR1H ;read chan. 1
Wait until conv. complete
STAA SWI ADRESULT ;store in result
Read result George W. Woodruff School of Mechanical Engineering, Georgia Tech