Transcript A/D Converter

ANALOG TO DIGITAL
CONVERTER
(ATD)
HCS12 Technical Training, Rev 2.0
Module 10- A/D Converter, Slide 1
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
ATD
1
ATD
0
12K
SRAM
256K
FLASEEPROM
SCI
1
SCI
1
Internal Bus
SPI 2 SPI 1
or
or
PWM
PWM PWM SPI 0
8
CH CH
CHAN
4-7
0-3
msCAN
4
or
IIC
msCAN
3
msCAN
2
BKP INT
HCS12 CPU
msCAN
1
BDLC
or
msCAN
0
MMI
SIM
CM BDM
MEBI
PIM PLL
PIT
4K
BYTES
EEPROM
ECT
8
CHAN
HCS12 Technical Training, Rev 2.0
Module 10- A/D Converter, Slide 2
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Analog to Digital
Converter
FEATURES:
• 8/10 Bit Resolution.
• 7 usec, 10-Bit Single Conversion Time.
• Sample Buffer Amplifier.
• Programmable Sample Time.
• Left/Right Justified, Signed/Unsigned Result Data.
• External Trigger Control.
• Conversion Completion Interrupt Generation.
• Analog Input Multiplexer for 8 Analog Input Channels.
• Analog/Digital Input Pin Multiplexing.
• 1 to 8 Conversion Sequence Lengths.
• Continuous Conversion Mode.
• Multiple Channel Scans.
HCS12 Technical Training, Rev 2.0
Module 10- A/D Converter, Slide 3
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
A/D Register
Map
HCS12 Technical Training, Rev 2.0
Module 10- A/D Converter, Slide 4
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
A/D Clock Select/ Prescaler
• Maximum A/D Clock = 2.0 MHz (MININUM A/D CLOCK = .5 MHz)
PRS0-PRS4
SYSTEM CLOCK
Divide
By 2
5-Bit Modulus Counter
Prescaler
A/D Clock
ATDCTL4(HI) - A/D CONTROL REGISTER
Address offset
$0004
SRES8 - A/D Resolution Select
1 = Select 8-bit Resolution
0 = Select 10-bit Resolution
SAMPLE TIME SELECT
SMP [1:0]
Sample Time
00
2 A/D Clock Periods
01
4 A/D Clock Periods
10
8 A/D Clock Periods
11
16 A/D Clock Periods
• 5-Bit Modulus Counter Prescaler
- Controlled by PR[4:0] in A/D Control Register 0
- Divides system clock by any integer from 2 to 64, inclusive(PRS value + 1)
- If PRS[4:0] = 0, then prescaler is bypassed
Note: PRS[4:0] must not make A/D Clock > 2 MHz.
HCS12 Technical Training, Rev 2.0
Module 10- A/D Converter, Slide 5
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Conversion Timing
A/D Clock
Always
2 Clocks
2, 4, 8, 16
Clocks
Conversion time calculation Examples:
(Assume 2MHZ A/D Clock)
Example 1:
Conversion Time = Initial Sample Time + Programmed Sample Time + Resolution Period
= 2 + 2 + 10 = 14 A/D Clocks
= 7uSec
Example 2:
Conversion Time = Initial Sample Time + Programmed Sample Time + Resolution Period
= 2 + 16 + 10 = 28 A/D Clocks
= 14uSec
HCS12 Technical Training, Rev 2.0
Module 10- A/D Converter, Slide 6
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
A/D Control Registers
ATDCTRL2 - A/D CONTROL REGISTER 2
ADPU - A/D Power-Up Enable/Disable
1 = Apply Power to A/D
0 = Reduce power by disabling A/D
AFFC - A/D Fast Conversion Complete Flag Clear
1 = Fast Flag clear sequence
0 = Normal Flag clear sequence
Address offset
$0002
ASCIE - A/D Sequence Complete Interrupt Enable
1 = Enable A/D Interrupts
0 = Disable A/D interrupts
ASCIF - A/D Sequence Complete Interrupt Flag
1 = Sequence complete interrupt
0 = no interrupts pending
AWAI - A/D Wait Mode
1 = Enable Conversion in CPU Wait
0 = Disable Conversion in CPU Wait
ETRIGLE - External Trigger Level/Edge Control
1 = Level Mode - Active Level Gate
0 = Edge Mode - Active Edge Mode
ETRIGP - External Trigger Polarity Control
1 = Active High Level or Rising Edge Active
0 = Active Low Level or Falling Edge Active
ETRIGE - External Trigger Mode Enable
1 = External Trigger Enabled
0 = External Trigger Disabled
HCS12 Technical Training, Rev 2.0
Module 10- A/D Converter, Slide 7
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
A/D Control Registers (Cont’d)
ATDCTRL3 - A/D CONTROL REGISTER 3
Address offset
$0003
FIFO - Result Register FIFO
1 = Result Registers do not Map to Conversion sequence
0 = Result Registers Map to Conversion Sequence
FRZ
Response
00
Ignore IFREEZE
01
Reserved
10
Finish conversion, then freeze
11
Freeze Immediately
Conversion Sequence Length Coding
HCS12 Technical Training, Rev 2.0
Module 10- A/D Converter, Slide 8
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
A/D Control Registers (Cont’d)
ATDCTRL5 - A/D CONTROL REGISTER 5
Address offset
$0005
CHANNEL SELECTION
DJM - Result Register Data Justification Mode
1 = Right Justified Mode
0 = Left Justified Mode
SCAN - Continuous Conversion Sequence Mode
1 = Select Continuous Conversion Sequence ( 4 or 8 )
0 = Select Single Conversion Sequence
( 4 or 8 times & stop )
DSGN - Signed/Unsigned Result Data Mode
1 = Select Signed Result
0 = Select Unsigned Result
MULT - Multiple Channel Sample Mode
1 = Select Multiple Channel Conversion Mode
0 = Select Single Channel Conversion Mode
• Note: A write to this register aborts current
conversion sequence and initiates a new
conversion sequence.
HCS12 Technical Training, Rev 2.0
Module 10- A/D Converter, Slide 9
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
0 0 0 = Chan 0
1 1 1 = Chan 7
Result Registers
Left Justified Result Data
Address Offset
$0010 - $0011
$001E - $001F
Right Justified Result Data
Address Offset
$0010 - $0011
$001E - $001F
HCS12 Technical Training, Rev 2.0
Module 10- A/D Converter, Slide 10
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
A/D Registers (Con’d)
ATDSTAT - A/D STATUS REGISTER
Address Offset
$0006
$0007
SCF - Sequence Complete Flag
- Set at end of conversion sequence in single conversion mode (SCAN = 0)
and at the end of first conversion sequence in continuous conversion mode (SCAN = 1).
- A write to this register clears SCF flag when (AFFC = 0).
ETORF - External Trigger Overrun Flag
-Sets if active edges occur while conversion sequence in progress.
FIFOR - Sets when the Result Register has been written before it was read by the CPU ( CCF was not cleared).
CC[2:0] - Conversion Counter
3-Bit counter that points to the next channel to be converted in 4 or 8 count sequence.
CCF7 -CCF0 - Conversion Complete Flags for individual A/D channels.
- Set upon end-of-conversion for each associated A/D channel.
- Cleared when associated A/D result register is read.
HCS12 Technical Training, Rev 2.0
Module 10- A/D Converter, Slide 11
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
A/D Port Register
PORTAD1 - A/D PORT Data Register
Address Offset
$000F
ADA7
ADA6
A
T
D
P
T
ADA5
ADA4
ADA3
ADA2
ADA1
ADA0
ATDDIEN - ATD Digital Input Enable
Note : Any port pin may be used as A/D or as GP Input.
HCS12 Technical Training, Rev 2.0
Module 10- A/D Converter, Slide 12
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.