Transcript Slide 1

Digital Design Flow

Digital Design Flow begins with specification of the design at various
levels of abstraction.

Design entry phase: Specification of design as a mixture of behavioral
Verilog code, instantiation of Verilog modules, and bus and wire
assignments
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Digital Design Flow
Design Entry in Verilog
Testbench in Verilog
module testbench ();
generate data;
process data;
endmodule
module design (. . .);
assign . . .
always . . .
compi (. . .)
endmodule
Behavioral Simulation
always (posedge clk)
begin . . . end
Comp1 U1 (. . .);
Comp2 U2 (. . .);
...
Compn Un (. . .);
if (…) bus = w;
else . . .
Assertion Verification
Formal Verification
Violation Report;
Time of Violation;
Monitor Coverage
Pass / Fail Report
Property Coverage
Counter Examples
Compilation and Synthesis
Analysis
Synthesis
C++ Classes,
Language Representation
Y=a&d&w
w=a&b|c
Routing and placement
Timing Analysis
1.6 ns
2 ns
Post-synthesis Simulation
Device Programming
 FPLD Design Flow
1010...
ASIC Netlist
Custom IC Layout
EDIF
or other netlists
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Digital Design Flow
Design Entry
Phase
Design Entry in Verilog
Testbench in Verilog
module testbench ();
generate data;
process data;
endmodule
module design (. . .);
assign . . .
always . . .
compi (. . .)
endmodule
Behavioral Simulation
Comp1 U1 (. . .);
Comp2 U2 (. . .);
...
Compn Un (. . .);
always (posedge clk)
begin . . . end
if (…) bus = w;
else . . .
Assertion Verification
Formal Verification
Violation Report;
Time of Violation;
Monitor Coverage
Pass / Fail Report
Property Coverage
Counter Examples
 FPLD Design Flow
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Digital Design Flow

Presynthesis verification: Generating testbenches for verification of the
design and later for verifying the synthesis output
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Digital Design Flow
Behavioral Simulation
Assertion Verification
Formal Verification
Violation Report;
Time of Violation;
Monitor Coverage
Pass / Fail Report
Property Coverage
Counter Examples
Compilation and Synthesis
Analysis
Synthesis
C++ Classes,
Language Representation
Y=a&d&w
w=a&b|c
Routing and placement
Timing Analysis
 FPLD Design Flow
(Continued)
2 ns
Presynthesis
Verification
1.6 ns
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Digital Design Flow

Synthesis process: Translating the design into actual hardware of a
target device (FPLD, ASIC or custom IC)
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Digital Design Flow
Behavioral Simulation
Assertion Verification
Formal Verification
Violation Report;
Time of Violation;
Monitor Coverage
Pass / Fail Report
Property Coverage
Counter Examples
Compilation and Synthesis
Analysis
Synthesis
C++ Classes,
Language Representation
Y=a&d&w
w=a&b|c
Routing and placement
Timing Analysis
Synthesis Process
 FPLD Design Flow
(Continued)
2 ns
1.6 ns
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Digital Design Flow

Postsynthesis simulation: Testing the behavioral model of the design
and its hardware model by using presynthesis test data
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Digital Design Flow
Testbench in Verilog
Timing Analysis
module testbench ();
generate data;
process data;
endmodule
1.6 ns
2 ns
Post-synthesis Simulation
Postsynthesis
Verification
Device Programming
ASIC Netlist
Custom IC Layout
EDIF
or other netlists
1010...
 FPLD Design Flow (Continued)
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Digital Design Flow

Digital Design Flow ends with generating netlist for an application
specific integrated circuits (ASIC), layout for a custom IC, or a program
for a programmable logic devices (PLD)
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Digital Design Flow
Testbench in Verilog
Timing Analysis
module testbench ();
generate data;
process data;
endmodule
1.6 ns
2 ns
Post-synthesis Simulation
Device Programming
ASIC Netlist
Custom IC Layout
EDIF
or other netlists
1010...
 FPLD Design Flow (Continued)
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Digital Design Flow
Digital Design
Flow
Design Entry
Testbench in Verilog
Design Validation
Compilation
and Synthesis
Postsynthesis
Simulation
Timing
Analysis
Hardware
Generation
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Verilog HDL


A language that can be understood by:
 System Designers
 RT Level Designers,
 Test Engineers
 Simulators
 Synthesis Tools
 Machines
Has become an IEEE standard
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The Verilog Language

The Verilog HDL satisfies all requirements for design and synthesis of
digital systems:



Supports hierarchical description of hardware from system to gate
or even switch level.
Has strong support at all levels for timing specification and
violation detection.
A hardware component is described by the module_declaration
language construct in it.
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The Verilog Language

The Verilog HDL satisfies all requirements for design and synthesis of
digital systems (Continued):




Description of a module specifies a component’s input and output
list as well as internal component busses and registers within a
module, concurrent assignments, component instantiations, and
procedural blocks can be used to describe a hardware component.
Several modules can hierarchically be instantiated to form other
hardware structure.
Simulation environments provide graphical front-end programs and
waveform editing and display tools.
Synthesis tools are based on a subset of Verilog.
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Elements of Verilog

We discuss basic constructs of Verilog language for describing a
hardware module.
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Elements of Verilog
Hardware
Modules
Primitive
Instantiations
Assign
Statements
Condition
Expression
Procedural
Blocks
Module
Instantiations
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Hardware Modules
Hardware
Modules
Modules
Primitive
Instantiations
Assign
Statements
Condition
Expression
Procedural
Blocks
Module
Instantiations
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Hardware Modules
module :
The Main
Component
of Verilog
Keyword
module
module module-name
Variables, wires, and
List of ports;
module parameters
Declarations
are declared.
...
Functional specification of module
...
Keyword
endmodule
endmodule
 Module Specifications
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Hardware Modules



There is more than one way to describe a Module in Verilog.
May correspond to descriptions at various levels of abstraction or to
various levels of detail of the functionality of a module.
We show a small example and several alternative ways to describe it in
Verilog.
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Primitive Instantiations
Hardware
Modules
Primitive
Primitive
Instantiations
Assign
Statements
Condition
Expression
Procedural
Blocks
Module
Instantiations
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Primitive Instantiations
a_sel
a
s_bar
s
b
Logic Gates
called
Primitives
w
b_sel
 A Multiplexer Using Basic Logic Gates
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Primitive Instantiations
module MultiplexerA (input a, b, s, output w);
wire a_sel, b_sel, s_bar;
not U1 (s_bar, s);
Instantiation
and U2 (a_sel, a, s_bar);
of Primitives
and U3 (b_sel, b, s);
or
U4 (w, a_sel, b_sel);
endmodule
 Primitive Instantiations
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Assign Statements
Hardware
Modules
Primitive
Instantiations
Assign
Statements
Condition
Expression
Procedural
Blocks
Module
Instantiations
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Assign Statements
Continuously
drives w with the
right hand side
expression
module MultiplexerB (input a, b, s, output w);
assign w = (a & ~s) | (b & s);
endmodule
 Assign Statement and Boolean
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Using Boolean
expressions to
describe the logic
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Condition Expression
Hardware
Modules
Primitive
Instantiations
Assign
Statements
Condition
Condition
Expression
Procedural
Blocks
Module
Instantiations
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Condition Expression
Can be used when
the operation of a
unit is too complex
to be described by
Boolean expressions
module MultiplexerC (input a, b, s, output w);
assign w = s ? b : a;
endmodule
 Assign Statement and Condition Operator
Useful in describing a
behavior in a
very compact way
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Very Effective in
describing complex
functionalities
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Procedural Blocks
Hardware
Modules
Primitive
Instantiations
Assign
Statements
Condition
Expression
Procedural
Blocks
Module
Instantiations
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Procedural Blocks
always
statement
Sensitivity list
module MultiplexerD (input a, b, s, output w);
reg w;
always @(a, b, s) begin
if (s) w = b;
else w = a;
Can be used when the
end
if-else
operation of a unit is
endmodule
statement
too complex to be
described by Boolean or
conditional expressions
 Procedural Statement
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Module Instantiations
Hardware
Modules
Primitive
Instantiations
Assign
Statements
Condition
Expression
Procedural
Blocks
Module
Module
Instantiations
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Module Instantiations
module ANDOR (input i1, i2, i3, i4, output y);
ANDOR
assign y = (i1 & i2) | (i3 & i4);
module is
endmodule
defined
//
module MultiplexerE (input a, b, s, output w);
wire s_bar;
not U1 (s_bar, s);
ANDOR U2 (a, s_bar, s, b, w);
ANDOR
endmodule
module is
 Module Instantiation
instantiated
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Module Instantiations
a
s
i1
i2
b
i3
i4
ANDOR
y
w
 Multiplexer Using ANDOR
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Component Description
in Verilog
Component
Description
Data
Components
Controllers
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Data Components
Component
Description
Data
Data
Components
Components
Controllers
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Data Components
Data
Components
Multiplexer
Flip-Flop
Counter
Full-Adder
Shift-Register
ALU
Interconnections
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Multiplexer
Data
Components
Multiplexer
Flip-Flop
Counter
Full-Adder
Shift-Register
ALU
Interconnections
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Multiplexer
Defines a Time Unit of 1 ns
and Time Precision of 100 ps.
`timescale 1ns/100ps
module Mux8 (input sel, input [7:0] data1, data0,
output [7:0] bus1);
assign #6 bus1 = sel ? data1 : data0;
endmodule
A 6-ns Delay
 Octal 2-to-1 MUX
is specified for all
values assigned to
bus1
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Selects its 8-bit
data0 or data1 input
depending on its
sel input.
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Flip-Flop
Data
Components
Multiplexer
Flip-Flop
Counter
Full-Adder
Shift-Register
ALU
Interconnections
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The Body of
always statement is
executed at the
negative edge of
the clk signal
Flip-Flop
Synchronous
reset input
`timescale 1ns/100ps
Flip-Flop
triggers on the
falling edge of
clk Input
module Flop (reset, din, clk, qout);
input reset, din, clk;
A Signal declared as a
output qout;
reg to be capable of
reg qout;
holding its values
between clock edges
always @(negedge clk) begin
if (reset) qout <= #8 1'b0;
else qout <= #8 din;
end
A Non-blocking
endmodule
 Flip-Flop Description
An 8-ns
Delay
Assignment
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Counter
Data
Components
Multiplexer
Flip-Flop
Counter
Full-Adder
Shift-Register
ALU
Interconnections
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A 4-bit modulo-16
Counter
Counter
4-bit
Register
`timescale 1ns/100ps
module Counter4 (input reset, clk,
output [3:0] count);
Constant
reg [3:0] count;
Definition
always @(negedge clk) begin
if (reset) count <= #3 4'b00_00;
else count <= #5 count + 1;
end
When count
endmodule
reaches 1111,
the next count
taken is 10000
 Counter Verilog Code
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Full-Adder
Data
Components
Multiplexer
Flip-Flop
Counter
Full-Adder
Shift-Register
ALU
Interconnections
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Full-Adder
A combinational
circuit
All Changes
Occur after 5 ns
`timescale 1ns/100ps
module fulladder (input a, b, cin, output sum, cout);
assign #5 sum = a ^ b ^ cin;
assign #3 cout = (a & b)|(a & cin)|(b & cin);
endmodule
 Full-Adder Verilog Code
One delay for
every output:
tPLH and tPHL
All Changes
Occur after 3 ns
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Shift-Register
Data
Components
Multiplexer
Flip-Flop
Counter
Full-Adder
Shift-Register
ALU
Interconnections
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Shift-Register
2 Mode inputs
m[1:0] form a
`timescale
2-bit number 1ns/100ps
An 8-bit
Universal
Shift Register
module ShiftRegister8
(input sl, sr, clk, input
[7:0] ParIn,
Case Statement
input [1:0] m, output
[7:0] ParOut);
With 4 reg
case-alternatives
and default Value
always @(negedge clk) begin
case (m)
m=0 : Does Nothing
0: ParOut <= ParOut;
1: ParOut <= {sl, ParOut [7:1]};
2: ParOut <= {ParOut [6:0], sr}; m=1,2: Shifts Right
and Left
3: ParOut <= ParIn;
default: ParOut <= 8'bX;
endcase
m=3 : Loads its Parallel
end
input into the register
endmodule
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Shift-Register (Continued)
`timescale 1ns/100ps
module ShiftRegister8
(input sl, sr, clk, input [7:0] ParIn,
input [1:0] m, output reg [7:0] ParOut);
Shift Right:
The SL input is
concatenated to
the left of
always @(negedge clk) begin
case (m)
0: ParOut <= ParOut;
ParOut
1: ParOut <= {sl, ParOut [7:1]};
2: ParOut <= {ParOut [6:0], sr};
3: ParOut <= ParIn;
default: ParOut <= 8'bX;
Shifting the
endcase
ParOut to the left
end
endmodule
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ALU
Data
Components
Multiplexer
Flip-Flop
Counter
Full-Adder
Shift-Register
ALU
Interconnections
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ALU
`timescale 1ns/100ps
module ALU8 (input [7:0] left, right, 2-bit mode Input
to select one of its
input [1:0] mode,
4 functions
output reg [7:0] ALUout);
always @(left, right, mode) begin
case (mode)
0: ALUout = left + right;
1: ALUout = left - right;
Add
Subtract
2: ALUout = left & right;
AND
3: ALUout = left | right;
OR
default: ALUout = 8'bX;
endcase
end
endmodule
 An 8-bit ALU
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ALU (Continued) The Declaration of
`timescale 1ns/100ps
ALUout both as
output and reg:
Because of
assigning it within
a Procedural Block
module ALU8 (input [7:0] left, right,
input [1:0] mode,
output reg [7:0] ALUout);
always @(left, right, mode) begin
Blocking
case (mode)
Assignments
0: ALUout = left + right;
1: ALUout = left - right;
2: ALUout = left & right;
3: ALUout = left | right;
default: ALUout = 8'bX;
default alternative
puts all Xs on ALUOut
endcase
if mode contains
end
anything but 1s and 0s
endmodule
 An 8-bit ALU
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Interconnections
Data
Components
Multiplexer
Flip-Flop
Counter
Full-Adder
Shift-Register
ALU
Interconnections
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Interconnections
Inbus
Aside Bside
8
8
select_source
Mux8 and ALU
examples forming a
Partial Hardware
8
8
ABinput
Function
8
Outbus
 Partial Hardware Using MUX8 and ALU
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Interconnections
A Set of parenthesis
enclose port
connections to the
instantiated modules
Instantiation of
ALU8 and MUX8
ALU8 U1 ( .left(Inbus), .right(ABinput),
.mode(function), .ALUout(Outbus) );
Mux8 U2 ( .sel(select_source), .data1(Aside),
.data0(Bside), .bus1 (ABinput));
and u2 : Code of The Partial Hardware Example
u1 Verilog
Instance Names
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Interconnections
The actual ports
of the instantiated
components
are excluded
An Alternative format
of port connection
ALU8 U1 ( Inbus, ABinput, function, Outbus );
Mux8 U2 ( select_source, Aside, Bside, ABinput );
 Ordered Port Connection
The list of local signals
in the same order as
their connecting ports
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Controllers
Component
Description
Data
Components
Controllers
Controllers
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Controllers
Decisions
Based on :Inputs ,
Outputs ,State
Issue Control Signal
Set Next State
Go to Next State
 Controller Outline
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Controllers


Controller:
 Is wired into data part to control its flow of data.
 The inputs to it controller determine its next states and outputs.
 Monitors its inputs and makes decisions as to when and what output
signals to assert.
 Keeps the history of circuit data by switching to appropriate states.
Two examples to illustrate the features of Verilog for describing state
machines:
 Synchronizer
 Sequence Detector
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Controllers
Controllers
Synchronizer
Sequence
Detector
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Synchronizer
Controllers
Synthesizer
Synchronizer
Sequence
Detector
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Synchronizer
Clk
adata
synched
 Synchronizing adata
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Synchronizer
`timescale 1ns/100ps
module Synchronizer (input clk, adata,
output reg synched);
always @(posedge clk)
if (adata == 0) synched <= 0;
If a 1 is Detected on
else synched <= 1;
adata on the rising
edge of clock,
endmodule
 A Simple Synchronization Circuit
synched becomes 1
and remains 1
for at least one
clock period
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Sequence Detector
Controllers
Synthesizer
Sequence
Sequence
Detector
Detector
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Sequence Detector
When the sequence
is detected, the w
Output becomes 1
and stays 1 for a
complete clock cycle
Searches on
it’s a input
for the
110 Sequence
a
If 110 is detected
on a, then w gets
1, else w gets 0.
w
clk
 State Machine Description
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Sequence Detector
A Moore Machine
Sequence Detector
The State in which
the 110 sequence is
detected.
States are named:
s0 , s1 , s2 , s3
reset
0
1
1
S0
0
0
0
1
S1
0
S2
0
S3
1
1
Initia
l
State
0
 Sequence Detector State Machine
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It Takes at least
3 clock periods to
get to the s3 state
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Sequence Detector
module Detector110 (input a, clk, reset, output w);
parameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11;
reg [1:0] current;
always @(posedge clk) begin
if (reset) current = s0;
else
case (current)
s0: if (a) current <=
s1: if (a) current <=
s2: if (a) current <=
s3: if (a) current <=
endcase
end
s1;
s2;
s2;
s1;
else
else
else
else
current
current
current
current
<=
<=
<=
<=
s0;
s0;
s3;
s0;
assign w = (current == s3) ? 1 : 0;
endmodule
 Verilog Code for 110 Detector
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Sequence Detector Description
Behavioral
of the
State Machine
module Detector110 (input a, clk, reset, output w);
parameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10,
s3=2'b11;
reg [1:0] current;
A 2-bit Register
always @(posedge clk) begin
if (reset) current = s0;
else
...........................
...........................
Parameter declaration
defines constants
s0, s1, s2, s3
 Verilog Code for 110 Detector
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Sequence Detector
...........................
...........................
always @(posedge clk) begin
if (reset) current = s0;
else
case (current)
At the
s0: if (a) current <= s1;
Absence of
s1: if (a) current <= s2;
a 1 on reset
s2: if (a) current <= s2;
s3: if (a) current <= s1;
endcase
end
 Verilog Code for 110 Detector
Verilog Digital System Design
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if-else statement
checks for reset
else
else
else
else
current
current
current
current
<=
<=
<=
<=
s0;
s0;
s3;
s0;
The 4 Case-alternatives
each correspond to a
state of state machine
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Sequence Detector
s1
0
s1:
a=1
s2
0
a=0
s0
0
if (a)
current <= s2;
else
current <= s0;
 State Transitions on Corresponding Verilog Code
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Sequence Detector
Outside of the
always Block:
A combinational
circuit
end
............................
............................
assign w = (current == s3) ? 1 : 0;
endmodule
 Verilog Code for 110 Detector
Verilog Digital System Design
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Assigns a 1 to w
output when
Machine Reaches to
s3 State
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