Transcript 投影片 1 - 可程式信號處理實驗室

Introduction of IP Generator
Speaker : Peng Chen Chi
National Central University
Department of Electrical Engineering
DSP Lab.
OUTLINE
Introduction
Behavioral Level IP
ADD/SUB IP Generator
Viterbi Decoder IP Builder
Reed-Solomon Code Generator
FFT IP Generator
Conclusion
National Central University
Department of Electrical Engineering
DSP Lab.
Introduction
What is IP ?
Intellectual Property (IP):Intellectual
property means products, technology,
software, etc.that have been protected
through patents, copyright, or trade
secrets.
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Department of Electrical Engineering
DSP Lab.
Introduction(cont.)
The electronic industry is moving toward the
design and implementation of entire systems
on a single chip (SoC).
Three types of reusable core (IP Core)
can be distinguished
The Soft Core is described using a high level
description language (i.e. VHDL or Verilog),
The Firm Core is described and synthesized
for specific library and finally
The Hard Core is described at the layout level.
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Department of Electrical Engineering
DSP Lab.
Behavioral Level IP
We can define a set of objective criteria for a BehavioralLevel IP (BL-IP) that guarantees the performances of the
block:
Blocks models must be uniform. This enables the extraction of
generic parameters and rules to define and compare different
implementations of functions.
BL-IP overhead development cost must be reasonable.
Flexibility is an important characteristic for BL-IP. The
environmental adaptation of BL-IP is done by setting a set of
parameters
BL-IP performance have to be tool independent. This
criterion introduces the concept of Universal HighLevel-Synthesis (U-HLS) tool.
To reach these goals, we propose to use an interface called a
generator and to specify the IP at the behavioral level
associated to the use of a methodology to simplify the IP
integrator task.
National Central University
Department of Electrical Engineering
DSP Lab.
Definition of IP Parameters
IP parameters have three different levels of
abstraction:
Algorithm selection parameters
Integrator parameters and constraints.
Synthesis tool parameters.
Parameters can interact with another from a
different level, and can be defined by
enumerations or bounds.
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IP Generator General Architecture
The interface enables the
specification of constraints and
parameters for a particular
block, that will help the
integrator in the definition of
the IP.
The estimator guides the
designer to a good
implementation of the function
according to the required
performances.
The U-HLS generator takes the
parameters defined through the
interface and generates an UHLS IP.
Derivators transform an U-HLS
IP to a tool specific description
of the BL-IP.
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Department of Electrical Engineering
DSP Lab.
Parameterized IP Design
Why to parameteriz IP?


Provide flexibility in interface and functionality
Facilitate verification
Parameterizable types

Logic/Algorithm functionality


Structural functionality


DCT,IDCT,DST,IDST
Bit-width,depth of FIFO,etc
Design Process functionality



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Test events
Event reports
Automatic check event
ADD/SUB IP Generator
Input parameter
Types of ADD/SUB




Ripple adder (RA)
Carry-lookahead adder (CLA)
Carry-select adder (CSA)
Carry-bypass adder (CBA)
Types of functionality



Addition
Subtraction
Addition/subtraction
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Department of Electrical Engineering
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ADD/SUB IP Generator
Input parameters
 word length
 Add register on (input/output/none)
 Performance optimization
 Area or timing
 Fixed stage sizing on architecture
 Fixed stage size for CLA, CSA, and CBA
 4-bit is suggested as stage size
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Department of Electrical Engineering
DSP Lab.
ADD/SUB IP Generator
Outputs



IP builder GUI
Synthesizable RTL code
Synthesis scripts
To apply the files ,can be immediately reported
to the user the results of timing,area and
power.

Test benches
Automatic output checking and error reporting
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ADD/SUB IP Generator
Documentation

The documentation part resumes all
the information about the IP generator .This
documentation must contain the function
description , a set of performances and
characteristics and the interface description.
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Department of Electrical Engineering
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Viterbi Decoder IP Builder
National Central University
Department of Electrical Engineering
DSP Lab.
Last Interface
National Central University
Department of Electrical Engineering
DSP Lab.
National Central University
Department of Electrical Engineering
DSP Lab.
National Central University
Department of Electrical Engineering
DSP Lab.
National Central University
Department of Electrical Engineering
DSP Lab.
Reed-Solomon code
Source
RS
encoder
Channel
Noise
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Department of Electrical Engineering
DSP Lab.
RS
decoder
Source
Reed-Solomon code word
n symbols ( m-bit)
………
2t redundancy symbols
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Department of Electrical Engineering
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…………
k information symbols
Reed-Solomon Code Generator
Design Spec.
Design parameter Manager
The RS Code Generator
consists of three parts
 Design Parameter
Module Integration Arrangement
HDL Output
Automated Synthesis Interface
Modules Synthesis Report
(Gate count, Speed , Power , memoty size)
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Manager
 Module Integration
Arrangement
 Automated Synthesis
Interface
Parameters of RS code Generator
Basic Parameters

Symbol Width (m)
 We often use m=8 for one symbol width, we also define
m=4 ,and m=7

Capability of Error Correction (t)
 The user can choose how many symbol can be
corrected.

Block Length (n)
 The user can decide the length of a code word. But the
maximum length is limited by symbol width (m)

Information Data (k)
 This parameter indicates the number of information
symbols within a block
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Department of Electrical Engineering
DSP Lab.
Parameters of RS code Generator
Advanced Parameters

Encoding Basis (eb)
We develop two architectures of RS encoding,
They have advantages such as area size and
processing speed on different application

Decoding Algorithm (db)
The generator has three RS decoding
algorithms to choose.

Folding Level (fd)
We can choose how many times of reusing
FFM (Finite Field Multiplication)
National Central University
Department of Electrical Engineering
DSP Lab.
Operation diagram of RS code generator
Input RS code symbol size m (m={4,7,8}) :8
Input RS code block length n ( n<2^8) :255
Input RS code correctable symbol t (t={2,8,10}) :10
==================================================================
Type 1:g(x) Base. It generates only encoder hardware.
Type 2:a(x) Base. It combines with encoder and syndrome module.
Input Encode code Type(1 or 2) : 1
==================================================================
(1)Don’t do anything
(2)Unfolding by 2 factor -This will increase area
(3)Folding by 2 factor
-This will increase speed
(4)Folding by 4 factor
-This will increase speed
Input Folding level (1,2,3,4):1
==================================================================
(1) Berlekamp-massy Algorithm
(2) Euclidean’s Algorithm
(3) PGZ Algorithm (only for t<3)
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Input RS
decoder
Algorithm(1,2,or
DSP Lab.
3) :1
Output files
RTL Code File


Rsdec.v:This file is top module of RS decoder and describes the decoder
processing.
Rsenc.v:This file is top module of RS encoder and describes the encoder
processing.
Test Bench File


TestEnc.v :this file is used to test encoder circuit
TestDec.v :this file is used to test decoder circuit
Synthesis Script File


Rsenc.script:Script file for RS encoder module
Rsdec.script:Script file for RS decoder module
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Department of Electrical Engineering
DSP Lab.
FFT IP Generator
利用Decimation In Frequency FFT的演
算法,分別搭配Radix-2,Radix-2/4,Radix2/4/8 ,Multiple-Path Delay
Communicator多管線的硬體架構以Soft
IP的程式結構方式去實現一個FFT的IP產
生器.可提供64~8192點的FFT Verilog 程
式碼.
National Central University
Department of Electrical Engineering
DSP Lab.
64Points Radix-2/4/8 FFT signal flow
R2
R-2/4
R-2/8
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Department of Electrical Engineering
DSP Lab.
National Central University
Department of Electrical Engineering
DSP Lab.
FFT IP Generator
輸入FFT 相關參數
FFT IP Generator
產生所對應之Verilog程式及所對應的Test bench檔
National Central University
Department of Electrical Engineering
DSP Lab.
The FFT IP Generator consists of three parts
Design Parameter Manager
Module Integration Arrangement
Automated Synthesis Interface
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Department of Electrical Engineering
DSP Lab.
Design Parameter Manager
In our FFT IP Generator, the parameters
given by the user are calculated
internally to analyse if the parameters
are valid.
If the input values are invalid, the
system will respond error messages to
the user.
National Central University
Department of Electrical Engineering
DSP Lab.
Module Integration Arrangement
Module Integration Arrangement
generates a circuit according to the
design parameters.Each module is
generated by one unit of the design
hierachy. This feature makes the
module easy to expand and maintain.
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Department of Electrical Engineering
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Automated Synthesis Interface
From the output HDL description, the
Automated Synthesis Interface Links
verilog-HDL file into synopsys synthesis
routines,
It is possible to describe the synthesis
routine like Verilog-HDL. The files are
called dc script files. To apply the
files ,can be immediately reported to
the user the results of timing,area,and
power.
National Central University
Department of Electrical Engineering
DSP Lab.
通訊系統所需要FFT點數對照表
通訊系統
IEEE802.11a
IEEE802.11g
ADSL
VDSL
DAB
DVB-T
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Department of Electrical Engineering
DSP Lab.
所需FFT點數
64
64
512
256,512,1024,2048,4096,8192
256,512,1024,2048
2048,8192
各點所需電路
64 Points： 2 * (Radix-2/4/8)
128 Points : Radix-2+2 *(Radix- 2/4/8)
256 Points: Radix-2/4+2 *(Radix-2/4/8)
512 Points: 3 * (Radix-2/4/8)
1024 Points : Radix-2+ 3 *(Radix-2/4/8)
2048 Points: Radix-2/4+3 *(Radix2/4/8)
4096 Points: 4 * (Radix-2/4/8)
8192 Points: Radix-2+4 *(Radix-2/4/8)
National Central University
Department of Electrical Engineering
DSP Lab.
FFT IP Generator Block
我們將每一個元件製成一個模組,利用物件導向的觀念
將所需要使用的元件呼叫進來,再把控制電路加進來,
即可完成一個64~8192點的FFT IP Generator
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Department of Electrical Engineering
DSP Lab.
FFT IP Generator 所產生之檔案
FFT 之可合成Verilog 程式碼
FFT_top.v
Test bench :FFT_tst.v
Test pattern:FFT_inp.dat
Synopsys dc script:FFT.dc
National Central University
Department of Electrical Engineering
DSP Lab.
GOAL
我們的IP generator能夠自動的對於不同的參
數值產生相對應的FFT code 此一IP generator
具有以下特性
1.提供一簡單之操作介面,減少使用者對於參數的設定
錯誤
2.標準檔案輸出,產生可程式化的Verilog code.
3.自動產生測試模組及測試向量,達到快速驗證之效能
4.提供一自動合成描述檔,能夠迅速的產生閘階層電路
5.合成結束後,提供關於指定參數之面積,速度及功率之報告
National Central University
Department of Electrical Engineering
DSP Lab.
Conclusion
Inputs
IP Generator
 Power dissipation, code size , application performance ,
die size ,etc
 Types,number ,and sizes of functional units, including
processor
 User defined instruction
Outputs
 RTL code and testbenches
 Synthesis and P&R Scripts
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Department of Electrical Engineering
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設計流程介紹
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Cell based Design Flow
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Department of Electrical Engineering
DSP Lab.