Transcript Integral Humanism

Gheorghe M. Ştefan
http://arh.pub.ro/gstefan/
- 2014 -
Veitch-Karnaugh diagrams
m0 = a’b’c’d’
m1 = a’b’c’d
m2 = a’b’cd’
m3 = a’b’cd
m4 = a’bc’d’
m5 = a’bc’d
m6 = a’bcd’
m7 = a’bcd
m8 = ab’c’d’
m9 = ab’c’d
...
m15 = abcd
Are based on the minimal Hamming distance
between adjacent cells
Veitch version
2014
Digital Integrated Circuits - week nine
2
2014
Digital Integrated Circuits - week nine
3
Karnaugh version
2014
Digital Integrated Circuits - week nine
4
Minimizing logic functions
smallest number, of rectangular
surfaces of 1’s, with maximal area,
containing 2i 1’s, and including all 1’s
2014
Digital Integrated Circuits - week nine
5
“don’t care”s
a’b +a’c
2014
b+c
Digital Integrated Circuits - week nine
6
V-K’s with included functions
Is a two-step process:
1. Only 1’s
2. 1’s become “don’t’ care”s
(bc’d + a’bc’ + b’c) + (acde + c’de’)
2014
Digital Integrated Circuits - week nine
7
Transition diagrams
2014
Digital Integrated Circuits - week nine
8
Moore version
2014
Digital Integrated Circuits - week nine
9
2014
Digital Integrated Circuits - week nine
10
Mealy version
2014
Digital Integrated Circuits - week nine
11
Verilog modules
Immediate Moore version for ‘bb detector’
2014
Digital Integrated Circuits - week nine
12
State transition function:
2014
Digital Integrated Circuits - week nine
13
Output transition function:
For the delayed version:
always @(posedge clock)
case(state)
init_state : out <= no;
. . .
2014
Digital Integrated Circuits - week nine
14
For the immediate Mealy version of ‘bb
detector’ only the output function is
different:
For the delayed version the change is similar as for Moore
version
2014
Digital Integrated Circuits - week nine
15
Automata are complex circuits
 The number of lines in the Verilog description:
 Are equal with the number of states for the behavioral
descriptions
 Are equal with the number of gates used for the structural
descriptions
 The transition diagrams have the size in
O(|Q| log |Q|)
Because they are complex we must keep them small
2014
Digital Integrated Circuits - week nine
16
State coding
First coding
Second coding
2014
Digital Integrated Circuits - week nine
17
First version:
2014
Second version:
Digital Integrated Circuits - week nine
18
Coding styles
 Minimal variation encoding:
successive states are coded with minimal Hamming
distance
 Reduced dependency encoding:
minimal Hamming distance for states preceded by
the same state
 Incremental encoding:
whenever possible successive state are coded by
incremented values
 One-hot state encoding:
one bit per state
2014
Digital Integrated Circuits - week nine
19
Minimal variation encoding
2014
Digital Integrated Circuits - week nine
20
Reduced dependency encoding
Reduced dependency on both, X0 and X1 has no solution
2014
Digital Integrated Circuits - week nine
21
Parasitic effects in automata
 Automata with asynchronous inputs
 Automata with asynchronous outputs
 Hazard generated by asynchronous inputs
 Propagation hazard
 Dynamic hazard
2014
Digital Integrated Circuits - week nine
22
Automata with
asynchronous inputs
If the input variable switches asynchronously the input
of the state register can vary in the prohibited time –
tsu + t+ +th
 No problems if only one bit switches:
00 -> 01 => 00 -> 01 or 00 -> 00
 Big problems if more than one bit switch:
01 -> 10 => 01 -> 10 or 01 -> 00 or 01 -> 11 or 01 -> 01
The automaton evolves wrongly in the state space
2014
Digital Integrated Circuits - week nine
23
The solution:
reduced dependency state coding
What can be done if there are state transitions depending
on two or more asynchronous input variable ?
2014
Digital Integrated Circuits - week nine
24
Asynchronous outputs:
hazard due to asynchronous inputs
2014
Digital Integrated Circuits - week nine
25
2014
Digital Integrated Circuits - week nine
26
Asynchronous outputs:
propagation hazard
2014
Digital Integrated Circuits - week nine
27
Avoiding propagation hazard
Partial protection
2014
Digital Integrated Circuits - week nine
Full protection
28
Dynamic hazard
Due to many-level combinational circuits (ex: carry
propagation)
2014
Digital Integrated Circuits - week nine
29
Fundamental limits
 The asynchronous input bits can be considered only
independently in distinct states
 Immediate Mealy automata with asynchronous inputs
can not have actual implementations (unpredictable
outputs)
 Delayed Mealy automata with asynchronous inputs
can not have actual implementations (the state and
outputs could evolve uncorrelated)
 Hazard free Moore with asynchronous inputs have no
actual solution (state must be encoded simultaneously
with minimal variation and reduced dependency)
2014
Digital Integrated Circuits - week nine
30
Home work 9
Problem 1:
2014
Digital Integrated Circuits - week nine
31