Transcript Integral Humanism

Gheorghe M. Ştefan
http://arh.pub.ro/gstefan/
- 2014 -
 Course: 3 hours/week
 Text book: http://arh.pub.ro/gstefan/0-BOOK.pdf
 Seminar: 2 hours every two weeks
 Laboratory: 2 hours every two weeks
 Grading:
 30% seminar
 40% home works
 30% final exam
 Mandatory: 50% from lab & seminar
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WHAT’S A DIGITAL SYSTEM?
 Framing the digital domain
 Defining a digital system
 Our first target
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Analog to Digital Conversion (ADC)
• s(t): a continuous, analog signal
• clock: periodic square wave with frequency fclock = 1/T
• sample rate: samples per second (SPS), is given by 1/T
• resolution: number of bits used to express the level (3 bits in our example)
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1
0
Both, sample rate and resolution are doubled
Commercial ADC:
• up to 6 GSPS
• 6 – 24 bits resolution (at 6 GSPS only 12 bits)
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Generic digital system
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What is computer science?
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Digital system. Formal definition
X {0,1}n
Y {0,1}m
S {0,1}q
DS = (X, Y, S, f, g)
is the n-bit input set
is the m-bit output set
is the q-bit internal state (state) set
f:(X × S) → S
g:(X × S) → Y
If
is the state transition function
is the output transition function
xt  X, yt  Y, st  S
st = f(xt-1, st-1) is a sequential function
yt = g(xt, st)
is a combinational function
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Digital Circuit: the simplest
embodiment of a Digital System
 Binary configurations:
 input: Xn-1, Xn-2, … X0
 output: Ym-1, Ym-2, … Y0
 state: Sq-1, Sq-2, … S0
with: Xi, Yj, Sk,  {0,1} coded with:
 0 Volt for 0
 1-2 Volt for 1
 combinational circuits
 registers
 clock signal
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Combinational circuit
On in all n-bit binary configurations must be considered
Output can change at any input bit switch : always @(*)
On out some (rarely all) of m-bit binary configurations are considered
tp: propagation time
shaded time interval: transition time from F(in1) to F(in2)
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The Register
tsu: set-up time
thold: hold time
tp: propagation time
from active edge of
clock to output
Tclock: the period of
the clock signal
… ti-1 ti ti+1 … : discrete
ticking time
shaded interval:
the input can change in
this time interval
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Digital system in Verilog HDL
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The content of file 0_parameter.v :
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Color code:
blue – reserved words
green – comments
orange - numbers
13
The result of synthesis
stateTransition combinational module is instantiated as stateTrans
outputTransition combinational module is instantiated as outTrans
fd is the register; its output goes forward to outTrans and backward
to close the loop though stateTrans module
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Our first target
Rare and isolated wrong pixels must be corrected. No video sensor is perfect.
s(t): the input sample at the moment t
s’(t): the corrected sample at the moment t
The algorithm: s’(t) = if
then
else
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(s(t)= 0)
(s(t-1) + s(t+1))/2
s(t)
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The error
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The actual timing
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To make the correction, three successive values:
in (t-3] in (t-2) in(t-1)
must be loaded as the internal state of the circuit.
The structure of the internal state consists of 3 sub-states:
State[11:0] = {ss3[3:0],ss2[3:0],ss1[3:0]}
State transition function:
state(t)
= {ss3, ss2, ss1}
state(t+1) = {ss2, ss1, in(t)}
Output transition function:
Out(t) = (ss2 = 0) ? (ss3+ss1)/2 : ss2
Results a latency of 2 clock cycles
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in = xxxx
clock
state[11:8] =
xxxx
state[7:4] =
xxxx
state[3:0] =
xxxx
+
/2
= 0?
x
xxxx
1
sel
0
out = xxxx
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in = 0111
clock
state[11:8] =
xxxx
state[7:4] =
xxxx
state[3:0] =
xxxx
+
/2
= 0?
x
xxxx
1
sel
0
out = xxxx
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in = 1001
clock
state[11:8] =
xxxx
state[7:4] =
xxxx
state[3:0] =
0111
+
/2
= 0?
0
xxxx
1
sel
0
out = xxxx
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in = 1010
clock
state[11:8] =
xxxx
state[7:4] =
0111
state[3:0] =
1001
+
/2
= 0?
0
xxxx
1
sel
0
out = 0111
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in = 1011
clock
state[11:8] =
0111
state[7:4] =
1001
state[3:0] =
1010
+
/2
= 0?
0
1000
1
sel
0
out = 1001
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in = 1100
clock
state[11:8] =
1001
state[7:4] =
1010
state[3:0] =
1011
+
/2
= 0?
0
1010
1
sel
0
out = 1010
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in = 1011
clock
state[11:8] =
1010
state[7:4] =
1011
state[3:0] =
1100
+
/2
= 0?
0
1011
1
sel
0
out = 1011
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in = 1010
clock
state[11:8] =
1011
state[7:4] =
1100
state[3:0] =
1011
+
/2
= 0?
0
1011
1
sel
0
out = 1100
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in = 1000
clock
state[11:8] =
1100
state[7:4] =
1011
state[3:0] =
1010
+
/2
= 0?
0
1011
1
sel
0
out = 1011
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in = 0101
clock
state[11:8] =
1011
state[7:4] =
1010
state[3:0] =
1000
+
/2
= 0?
0
1001
1
sel
0
out = 1010
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in = 0011
clock
state[11:8] =
1010
state[7:4] =
1000
state[3:0] =
0101
+
/2
= 0?
0
0111
1
sel
0
out = 1000
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in = 0010
clock
state[11:8] =
1000
state[7:4] =
0101
state[3:0] =
0011
+
/2
= 0?
0
0101
1
sel
0
out = 0101
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in = 0010
clock
state[11:8] =
0101
state[7:4] =
0011
state[3:0] =
0010
+
/2
= 0?
0
0011
1
sel
0
out = 0011
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in = 0000
clock
state[11:8] =
0011
state[7:4] =
0010
state[3:0] =
0010
+
/2
= 0?
0
0010
1
sel
0
out = 0010
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in = 0101
clock
state[11:8] =
0010
state[7:4] =
0010
state[3:0] =
0000
+
/2
= 0?
0
0001
1
sel
0
out = 0010
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in = 0111
clock
state[11:8] =
0010
state[7:4] =
0000
state[3:0] =
0101
+
/2
= 0?
1
0011
1
sel
0
out = 0011
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in = 1001
clock
state[11:8] =
0000
state[7:4] =
0101
state[3:0] =
0111
+
/2
= 0?
0
0011
1
sel
0
out = 0101
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Simulation
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Simulation (cont)
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Synthesis: top level
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Synthesis: second level
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Synthesis: third level
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The functions involved
in digital pixel correction
 The predicate function - (ss2 = 0) - used to detect the
wrong pixel
 The addition function , used to compute the interpolation
 The division by 2 function, used to compute the
interpolation
 The selection function, according to the result of the
predicate function select the result of interpolation or the
current value
 The storage function, triggered by the active edge of
clock, used to store the internal state of the system
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The first crossing through the matter
Main targets:
 Form behavioral to structural description in Verilog
 Working with simple combinational functions
 Learning about the internal structure of register
 Simple applications
 Provide the motivation for:
 Understand the transistor level description of a logic circuit
 Designing digital systems using digital circuits
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DIGITAL CIRCUITS
 Combinational circuits
 Zero circuit
 Selection circuit (multiplexor)
 Adder
 Divider
 Sequential circuits
 Elementary latches
 Clocked latches (transparent on the active level)
 Master-Slave flip-flops (triggered by the active edge)
 Register
 Applications
 Shift register
 Counter
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Combinational circuits
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x
y
xy
(xy)’
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
x
y
x+y
(x+y)’
0
0
0
1
0
1
1
0
1
0
1
0
1
1
1
0
x
y
xy
(xy)’
0
0
0
1
0
1
1
0
1
0
1
0
1
1
0
1
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Zero circuit: a n-input NOR
fan-in: number
of inputs of a
logic circuit
depth: number
of logic levels of a
logic circuit
size: the total
number of inputs
in all the circuits
fan-in = 2 fan-in = n
depth = 1 depth = 1
size = 2
size = n
2014
fan-in = 8
depth = 7
size = 14
fan-in = 8
depth = 3
size = 14
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Selection circuit (multiplexer)
out = sel in1 + sel’ in0
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Behavioral:
Structural:
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 Synthesis result for n = 4
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Adder
For n=1, results the one-bit adder . The logic expressions are
sum = a  b  c = (a  b)  c
carry = a b + c (a  b)
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sum =
=
=
=
=
carry
=
=
2014
a’b’c + a’bc’ + ab’c’ + abc
a’(b’c + bc’) + a(b’c’ + bc)
a’(b  c) + a(b  c)’
a  (b  c)
a  b  c
= a’bc + ab’c + abc’ + abc=
(a’b+ab’)c+ab(c’+c)=
(a  b)c + ab
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Integer divide by 2 == right shift
 Integers
 Positive integers: from 8’b0000_0000 = 0
to 8’b1111_1111 = +255
 Signed integers: from
8’b1_0000000 = -128
through 8’b0_0000000 = 0
to
8’b0_1111111 = +127
Negative integer is the positive one, complemented+1
+127=0_1111111 ->1_0000000+1=1_0000001=-127
 Divide by 2
 For positive integers: logic right shift (with 0 input)
8’b1001_1100 (156) => 8’b0100_1110 (78)
 For signed integers: arithmetic right shift (with sign input) - sign
is preserved
8’b1_1011001(-70) => 8’b1_1101100 (-35)
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Home work 1
Problems from 2.1 to 2.7; see Text Book at
http://dcae.pub.ro/gstefan/0-BOOK.pdf
Send your home work as a one-file word document to
[email protected]
With the subject:
CID_42x_LastName_FirstName_TCy
Example:
CID_421_Popescu_Ion_TC4
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