Transcript VGA DR1 - University of Melbourne

Radio-Frequency Integration Technology – RFIT 2005
A 2.7mW linear-in-dB VGA with
60dB tuning range and
two DC offset cancellation loops
Chien M. Ta
Chee Hong Yong
Wooi Gan Yeoh
Nov. 30 – Dec. 2, 2005
Institute of Microelectronics
Outline
• Introduction
• Specifications
• Circuit description
• Measurement results
• Concluding remarks and future works
• Acknowledgement
Page 2
Introduction
Motivation
• A Direct Conversion Receiver for Ultra-Wideband
communications
Objective
• A low-power Variable Gain Amplifier with DC Offset
Cancellation mechanism
Page 3
Specifications
Specification
Technology
Power supply
Value
0.18-μm bulk CMOS
1.8V
Bandwidth
> 100MHz
Low cutoff frequency
< 500kHz
Output swing
DC offset cancellation
Power consumption
Page 4
Condition
@ all gain levels
1V
Peak-to-peak
differentially
Output DC offset <5mV
@60dB gain,
10mV input offset
As low as possible
Architecture
LPF
_
IN
Fixed-gain
+
LPF
Variable-gain
_
OUT
+
Adder
Variable-gain
Adder
V-to-I converter
Control voltage
Two DC offset cancellation loops at the input and the output of
the VGA to suppress DC offset in the input signal and DC offset
caused by mismatches in the circuit itself.
Page 5
DC offset cancellation
LPF
_
Fixed-gain
+
Adder
Output DC offset is extracted and negatively fed back to cancel
the DC offset at the input of the fixed gain block.
Page 6
Fixed-gain stage
• Differential pair with degenerative
resistor: simple, stable, and linear
OUT1
OUT2
IN1
IN2
Is
Page 7
Is
• Split tail current: save voltage
headroom
• Issues: matching between the
components (solved by
interdigitizing)
Variable-gain stage
OUT1
OUT2
IN2
• Gilbert cell with degenerative
resistors: large gain range
(30dB linear-in-dB gain range)
IN1
IN1
AGilbert
Is1
Is1
Is2
Cell


I s1 
I s2

Is2
• Split tail current: save voltage
headroom
• Issues: matching between the
components (solved by
interdigitizing)
Vc
Page 8
Is2
Is1
V-to-I converter
Gain tuning curve
G a in tu n in g c u rv e
60.00
50.00
G ain (d B )
40.00
30.00
20.00
10.00
0.00
50 M H z
100M H z
-10.00
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
C o n tro l vo lta g e (V )
• Gain can be tuned linear-in-dB from -3dB to 57dB (the
specification is from 0dB to 60dB) when the control voltage
is varied from 0.2V to 0.9V
Page 9
Frequency response
Frequency response
70.00
60.00
50.00
Vc = 0.2V
40.00
Vc = 0.3V
Gain (dB)
Vc = 0.4V
30.00
Vc = 0.5V
Vc = 0.6V
20.00
Vc = 0.7V
Vc = 0.8V
10.00
Vc = 0.9V
0.00
Vc = 1.0V
-10.00
-20.00
-30.00
0.10
1.00
10.00
100.00
1000.00
Frequency (MHz)
• Low cutoff frequency at 600kHz (specification is <500kHz)
• 3-dB bandwidth of 130MHz (specification is >100MHz)
Page 10
DC offset cancellation
20
• Output DC offset is below
20mV for input DC offset up
to 40mV and below 10mV
for input DC offset up to
10mV
O utput D C offs et (m V )
15
10
5
0
-5
-10
0
5
10
15
20
25
30
35
Input D C offs et (m V )
Page 11
V c = 0.2 V
V c = 0.3 V
V c = 0.4 V
V c = 0.5 V
V c = 0.6 V
V c = 0.7 V
V c = 0.8 V
V c = 0.9 V
V c = 1.0 V
40
Summary of the design
Condition
Technology
Specification
Measurement
0.18-μm bulk CMOS
Power supply
1.8V
Power consumption
1.8V
2.7mW
Gain
0dB to 60dB
-3dB to 57dB
Bandwidth
> 100MHz
130MHz
Low cutoff frequency
< 500kHz
500kHz – 600kHz
Peak-to-peak
differentially
1V
1V
@60dB gain,
10mV input offset
<5mV
<10mV
Output swing
Offset cancellation
IIP3
-29dBm
Page 12
Concluding remarks and Future works
What have been achieved?
• A functional VGA architecture with two DC offset cancellation loops
• Tunable gain in dB-linear fashion with respect to the control voltage
• Maximum gain is as high as 57dB
• Satisfactory bandwidth of 130MHz
• Very low power consumption, 2.7mW
• Very small die area, 243μm x 264μm (0.064mm2)
What to do next?
• Improve the linearity by redesigning the last stage of the VGA; more
power consumption is needed
• Improve noise performance of the VGA by carefully redesigning the
first stage
• Reduce mismatch in the layout to get better DC offset cancellation
Page 13
Acknowledgement
• Dr. Lin Fujiang for coordinating the project
• Dr. Zheng Yuanjin, Mr. Ben Choi, Mr. Teo Tee Hui, and Mr.
Wong Sheng Jau for their advice during the design
• Ms. Wu Ye and Mr. Ram Chandra Yadav for reviewing the
paper
• IME management
Page 14
THANK YOU
Page 15
Benchmarking
Reference
Technolog
y
Supply
Hung Yan Cheung
et al.
CMOS
0.35um
3V
7mW
(AGC)
S. Otaka et al.
BiCMOS
fT = 20GHz
3V
36mW
(w/Buffer)
T. Yamaji et al.
CMOS
0.25um
2.5V
11mA
J. J. F. Rijns
CMOS
0.8um
5V
5mA
G. S. Sahota and
C. J. Persico
BiCMOS
3.6V
12mA
43.2mW
W. C. Song et al.
CMOS
0.35um
3V
10.8mA
32.4mW
This work
CMOS
0.18um
1.8V
1.5mA
2.7mW
(excluding
buffer)
Page 16
Current
Power
Area
1mm2
0.175mm2
BW
Gain
Linearity
Noise Figure
Year
20MHz
-30dB to
50dB
THD = 40dBc
50MHz to
500MHz
-35dB to
43dB
-38dBm @ 43dB
-8dBm @ -35dB
<5dB
2000
30MHz to
210MHz
-35dB to
55dB
P1dB=-40dBm @ 55dB
P1dB=-8dBm @ -35dB
IIP3=-28dBm @ 55dB
IIP3=7dBm @ -35dB
8dB @ max
gain
2002
THD  -60dB
15MHz
(Cload = 7pF)
2001
1996
300MHz
-45dB to
45dB
1997
580um x
660um
200MHz
-50dB to
50dB
10dBm @ -50dB
-30dBm @ 50dB
2000
243μm x
264μm
130MHz
-3dB to
57dB
-49dBm @ 57dB
-29dBm @ 7dB
2005