EECT 7327 - Data Converters
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Transcript EECT 7327 - Data Converters
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Switched-Capacitor Circuits
–1–
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Continuous-Time Integrator
t
1
vo t = v in ξ dξ
R1C2 -∞
C2
R1
Vi
Hs =
Vo
1 1
Vo
s = -
Vi
R
C
1 2 s
= R1C2
C2
Goal:
Vi
SC
Vo
Approach: emulating resistors with switched capacitors
–2–
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Concept of Switched Capacitor
Ф2
R
VA
VB
Non-overlapping
two-phase clock
Ф2
VA
VB
Ф1
i
i=
C
<i>
Ф1
Ф1
1
VA - VB
R
i =
R eq =
T
C
q C
= VA - VB
T T
so, = R eq,1 C2 =
Ф2
C
T
C2 = T 2
C1
C1
•
A switched capacitor is a discrete-time “resistor”
•
RC time constant set by capacitor ratio C2/C1 (match considerably better
than R and C) and clock period T (flexibility)
–3–
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Switched Capacitors
Shunt-type
Ф1
Series-type
Ф2
VA
Ф1
VB
C
VA
VB
Ф2
C
Ф2(Ф1)
C
Ф1
Ф2
Ф1
Ф2
Ф1
Ф2
Ф2
VA
VB
Ф1(Ф2)
2-phase clock
Stray-insensitive
Ф1
•
Shunt- and series-type SCs are simple and cheap to implement
•
Stray-insensitive SC requires 2 more switches, what’s the advantage
besides being more flexible (i.e., w/ or w/o the T/2 delay)?
–4–
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Discrete-Time Integrator (DTI)
Shunt-type
Series-type
C2
Ф1
Ф2
Ф2
Ф1
Vi
Vo
C2
C1
Vi
Vo
C1
2-phase clock
Ф1
Ф2
Ф1
Ф2
Ф1
Ф2
What are the VTFs (z-domain) of these DTIs, assuming no parasitic
capacitance is present?
–5–
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Shunt-Type DTI
Ф1
(sample)
T
C2
Ф1
Vi
Vo
C1
vi(t)
(n-1)
0
Ф2
Ф1
Ф2
Ф1
(n)
Ф2
t
(n+1)
Ф2
(update)
C2
vo(t)
(n+1)
(n)
Vi
Vo
C1
0
t
(n-1)
Charge conservation law (ideal):
Total charge on C1 and C2 during Ф1→ Ф2 transition must remain unchanged!
–6–
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Shunt-Type DTI
Ф1
(sample)
Ф2
(update)
C2
Vi
Vo
C1
Q φ = V n C
1
i
1
2
Vi
Vo
C1
Q φ = 0 C
- Vo n C 2
Q φ = Q φ
1
C2
2
1
- Vo n +1 C 2
⇒ Vi n C1 - Vo n C 2 = 0 C1 - Vo n +1 C 2
Vi z C1 - Vo z C 2 = -z Vo z C 2
Vo z
C1 z -1
H z =
=Vi z
C2 1- z -1
–7–
C1 z -1/2
or C 2 1- z -1
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Series-Type DTI
T
Ф1
(sample/update)
Ф2
(reset C1)
Ф1
vi(t)
Ф2
(n-1)
0
Ф2
Ф1
Ф2
Ф1
(n)
Ф2
t
C2
(n+1)
Ф1
C1
Vi
vo(t)
Vo
(n)
(n-1)
0
t
(n+1)
VTF:
H z =
Vo z
C 1
=- 1
Vi z
C2 1- z -1
–8–
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Stray Capacitance
Shunt-type
Ф1
Series-type
Ф2
C2
Ф2
C2
Ф1
A
C1
Vi
Vo
Vi
C1
A
C2
=4
C1
Cu
Cu
Cu
• Strays derive from D/S diodes and
wiring capacitance
• VTF is modified due to strays
Cu
C1
Vo
Cu
• Strays at the summing node is of no
significance (virtual ground)
C2
–9–
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Stray-Insensitive SC Integrator
C2
Ф2(Ф1) A
C1
Ф2
B
Vi
Vo
Ф1(Ф2)
Ф1
“Inverting”
VTF:
C 1
H z = - 1
C2 1- z -1
“Non-inverting”
VTF:
C1 z -1
H z = +
C2 1- z -1
•
Capacitors can be significantly sized down to save power/area
•
Sizes are eventually limited by kT/C noise, mismatch, etc.
– 10 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
SC Amplifier
Ф1
C2
Ф1
Vi
C1
VTF:
H z = +
Vo
Ф2
•
Non-integrating, memoryless (less the delay)
•
Used in many applications of parametric amplification
– 11 –
C1 -1
z
C2
Data Converters
EECT 7327
Switched-Capacitor Circuits
SC Applications
– 12 –
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
CT Filter
R
L
Vi
C
RLC prototype
Vo
R2
R4
CA
R1
R
R
CB
R3
Vi
Vo
– 13 –
Active-RC
Tow-Thomas
CT biquad
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
SC DT Filter
R2
R4
CA
R1
R
CB
R
Active-RC
Tow-Thomas
CT biquad
R3
Vi
Vo
C2
C4
CA
Ф2
C1
Ф2
Ф1
Ф1
C3
Ф2
Vi
CB
Ф2
Ф2
Vo
Ф1
Ф1
Ф2
Ф1
– 14 –
SC DT
biquad
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Sigma-Delta (ΣΔ) Modulator
CI
Ф1
CS
Ф2
Vi
Do
Ф2
+VR
-VR
Ф1
1-b
DAC
DTI + 1-bit comparator + 1-bit DAC = first-order ΣΔ ADC
– 15 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Pipelined ADC
Φ2
Φ1
C1
Φ1
C2
Vi
-VR/4
Vo
Φ1
VR/4
-VR
0
VR
1.5-b
DAC
Φ2
SC amplifier + 2 comparators + 3-level DAC = 1.5-bit pipelined ADC
– 16 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
SC Common-Mode Feedback
Vo+
R
A
R
Vo-
R
A
Vo-
R
Vcmc
Vcmc
VBias
Vo+
Vcm
Vcm-VBias
CM sense amp can be replaced by a floating voltage source since the gain
through the main op-amp is high enough.
– 17 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
SC Common-Mode Feedback
Ф2
Ф1
Vcm
Vo+
C
Ф2
A
0.2C Ф1
VBias
Vo-
C
Ф2
0.2C Ф1
Vcm
Vcmc
Ф1
Ф2
Vcm-VBias
Vo-
Vcm-VBias
A
Vcmc
– 18 –
Vo+
Data Converters
EECT 7327
Switched-Capacitor Circuits
Noise in SC Circuits
– 19 –
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Noise of CT Integrator
H1(f)
C
C
VN12
R
Vi
R
Vo
Vo
VN22
VoN
2
H2(f)
2
2
VN12
VN2 2
=
f H1 f df +
f H2 f df +...
Δf
Δf
Noise in CT circuits can be simulated with SPICE (.noise)
– 20 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Noise of SC Integrator
C2
Ф1
C1
Ф2
Vi
Vo
Ф2
Ф1
Ф1
Ф2
Ф1
Ф2
Ф1
Ф2
SC circuits are NOT noise-free! Switches and op-amps introduce noise.
– 21 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Sampling (Ф1) Ideal Voltage Source
VN12
R1
C1
VN22
Vi
R2
VN φ1 =
2
∞
0
VN12
2
VN2 2
f +
f H1 f df
Δf
Δf
2
∞
= 4kTR1 + 4kTR 2
0
=
1
df
1+ j2πf R1 +R 2 C
kT
C
•
Noise is indistinguishable from signal after sampling
•
The noise acquired by C1 will be amplified in Ф2 just like signal
– 22 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Integration (Ф2)
H34(f)
C2
VN32
C1
VN42 R4
Vo
R3
VN52
H5(f)
VN3 2
2
2
VN5 2
VN4 2
VN φ2 =
f +
f H34 f df +
f H5 f df +...
Δf
Δf
Δf
2
2
C
VoN2 = 1 VN2 φ1 + VN2 φ2
C2
No simulator can directly simulate the aggregated output noise!
– 23 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Sampling (Ф1) Noise – Cascaded Stages
C2
Ф2
C1
C2'
Ф1
Ф1
C1'
Ф2
Ф2
Vi
Vo
Ф1
Ф2
Ф2
Ф1
C2
VN32
R3
C1
VN42 R4
VN12
VN52
R1
C 1'
VN22
R2
•
Finite op-amp BW limits the noise bandwidth, resulting in less overall kT/C noise
(noise filtering).
•
But parasitic loop delay may introduce peaking in freq. response, resulting in more
integrated noise (noise peaking).
– 24 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Sampled Noise Spectrum
CT
PSD
0
fs
2fs
Alias
DT
PSD
0
fs/2
fs
3/2fs
•
Total integrated noise power remains constant
•
SNR remains constant
– 25 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Non-ideal Effects in
SC Circuits
– 26 –
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Non-ideal Effects in SC Circuits
• Capacitors (poly-poly, metal-metal, MIM, MOM, sandwich, gate cap,
accumulation-mode gate cap, etc.)
– PP, MIM, and MOM are linear up to 14-16 bits (nonlinear voltage
coefficients negligible for most applications)
– Gate caps are typically good for up to 8-10 bits
• Switches (MOS transistors)
– Nonzero on-resistance (voltage dependent)
– (Nonlinear) stray capacitance added (Cgs, Cgd, Cgb, Cdb, Csb)
– Switch-induced sampling errors (charge injection, clock feedthrough,
junction leakage, drain-source leakage, and gate leakage)
• Operational amplifiers
– Offset
– Finite-gain effects (voltage dependent)
– Finite bandwidth and slew rate (measured by settling speed)
– 27 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Non-ideal Effects of
Switches
– 28 –
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Nonzero On-Resistance
C
…
VGS
Ron
Ф
PMOS
NMOS
VTp
CS
Vout
VTn
CMOS
Ф
0
…
CS
R on -1 = μCox
Ф
Vout
VDD
W
VDD - Vth - Vout
L
•
FET channel resistance (thus tracking bandwidth) depends on signal level
•
Usually (RonCS)-1 ≥ (3-5)·ω-3dB of closed-loop op-amp for settling purpose
– 29 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Clock Bootstrapping
Ф
Ф1 Ф2
…
VDD
CS
In
Ф
Out
M1
CMOS
Bootstrapped NMOS
•
Small on-resistance leads to large switches → large parasitic caps and
large clock buffers
•
Clock bootstrapping keeps VGS of the switch constant → constant onresistance (body effect?) and less parasitics w/o the PMOS
– 30 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Simplified Clock Bootstrapper
Ф1
Ф2
VDD
In
Pros
Out
M1
• Linearity
VDD
• Bandwidth
Ф2
M2
Ф2
Cons
• Device reliability
Ф2
C
Ф1
• Complexity
Ф1
Out
M1
Ф2
In
VSS
– 31 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Switch-Induced Errors
Ф
Zi
Cgs
Cgd
Vout
Vin
Qch
• Clock feedthrough
• Charge injection
CS
Channel charge injection and clock feedthrough (on drain side) result in
charge trapped on CS after switch is turned off.
– 32 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Clock Feedthrough and Charge Injection
Ф
VDD
Zi
Cgs
Cgd
Ф
Vout
Vin
Qch
Vin+Vth
0
CS
Switch on
Switch off
•
Both phenomena sensitive to Zi, CS, and clock rise/fall time
•
Offset, gain error, and nonlinearity introduced to the sampling
•
Clock feedthrough can be simulated by SPICE, but charge injection
cannot be simulated with lumped transistor models
– 33 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Clock Rise/Fall-Time Dependence
Ф
VDD
Zi
Cgs
Cgd
Ф
Vout
Vin
Qch
0
CS
Switch on
Clock feedthrough
Fast turn-off
Slow turn-off
ΔV = -
ΔV = -
Cgs
Cgs + CS
Cgs
Cgs + CS
Vin+Vth
VDD
Vin + Vth
– 34 –
Switch off
Charge injection
ΔV = -
Cox WL VDD - Vth - Vin
2 Cgs + CS
ΔV = 0
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Dummy Switch
Ф
Vin
W
L
Ф
W
2L
Vout
CS
•
Difficult to achieve precise cancellation due to the nonlinear
dependence of ΔV on Zi, CS, and clock rise/fall time
•
Sensitive to the phase alignment between Ф and Ф_
– 35 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
CMOS Switch
Ф
Vin
Vout
Ф
CS
Same size for
P and N FETs
•
Very sensitive to phase alignment between Ф and Ф_
•
Subject to threshold mismatch between PMOS and NMOS
•
Exact cancellation occurs only for one specific Vin (which one?)
– 36 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Differential Signaling
Ф
Vip
Vop
M1
CSp
Ф
Vin
Balanced diff. input
Von
M2
CSn
•
Signal-independent errors (offset) and even-order distortions cancelled
•
Gain error and odd-order nonlinearities remain
– 37 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Switch Performance
On-resistance: R on
1
μCox
W
VDD
L
L2
L2
μQ ch
Vth Vi μCox WL VDD Vth Vi
Bandwidth:
BW
μQ
1
2 ch
Ron CS L CS
Charge injection:
ΔV
1 Qch
2 CS
Performance FoM:
ΔV 1 Qch L2CS L2
≈
=
BW 2 CS μQch 2μ
Technology scaling improves switch performance!
– 38 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Leakage in SC Circuits
Φ1 = “high”, Φ2 = “low”
Ф2
Ф2
C1
Vx
Vi
Ф1
Ф1
Vo(t)
C2
I2
I1
I3
Vo
Ф1
A0
Ф1
Ф2
0
VB
•
•
•
•
Ф2
I1 – diode leakage (existing in the old days too)
I2 – sub-threshold drain-source leakage of summing-node switch
I3 – gate leakage (FN tunneling) of amplifier input transistors
Leakage currents are highly temperature- and process-dependent; the
lower limit of clock frequency is often determined by leakage
– 39 –
t
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
DS Leakage
Ф2
CS+
Ф1
Ф1e
Vi+
Vo+
Vi-
VoФ1
CS
-
M1+
Ф2
0.13-μm CMOS
A0 = Gm·Ro = 90dB
Ro ≈ 2MΩ
Rleak ≈ 0.6V/3μA
≈ 0.2MΩ
• A0 = Gm·(Rleak//Ro)
≈ 70dB
Ф2e
Ф2e
M1-
Ф1e
•
•
•
•
CS+
VDD
VDD
CS-
VDD = 1.2V
Φ
M2
Ileak
M3
Φ
Φ
Φ
In
Out
M1
Φ
In
VSS = 0V
– 40 –
Φ
VDD
Φ
Φ
Φ
Φ
M4
Out
M1
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Gate Leakage
IGS ∝ WL exp -t ox exp VGS
•
Direct tunneling through the thin gate oxide
•
Short-channel MOSFET behaves increasingly like BJT’s
•
Violates the high-impedance assumption of the summing node
– 41 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Switch Size Optimization
• To minimize switch-induced error voltages, small transistor size,
slow turn-off, low source impedance should be used.
• For fast settling (high-speed design), large W/L should be used, and
errors will be inevitably large as well.
Guidelines
• Always use minimum channel length for switches as long as
leakage allows.
• For a given speed, switch sizes can be optimized w/ simulation.
• Be aware of the limitations of simulators (SPICE etc.) using lumped
device models.
– 42 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Non-ideal Effects of
Op-Amps
– 43 –
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Non-ideal Effects of Op-Amps
• Offset
• Finite-gain effects (voltage dependent)
• Finite bandwidth and slew rate (measured by settling
speed)
– 44 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Offset Voltage
C2
C1
Ф1
Q φ = V n C
Ф2
1
Vi
i
1
+ Vo n - Vos C 2
Vo
Ф2
Ф1
Q φ = -V
Vos
2
os
C1 + Vo n +1 - Vos C 2
C
Vi = 0 ⇒ Vo n +1 - Vo n = 1 Vos
C2
Vo(t)
Ф1
Ф2
Ф1
0
C1 z -1
Vo z =
V z
-1 i
C2 1- z
Ф2
t
Vi = 0
– 45 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Autozeroing
Ф1
Q φ = V n - V
1
C2
C1
Ф1
Vi
Ф2
i
Q φ = -V
Ф1
2
os
os
C1 - VosC 2
C1 + Vo n - Vos C 2
Vo
Ф2
Vos
H z =
Vo z C1
=
Vi z C2
•
Also eliminates low-frequency noise, e.g., 1/f noise
•
A.k.a. correlated double sampling (CDS)
– 46 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Chopper Stabilization
Vn2
Vi
A
B
A1
A2
Vo
fC
1
-1
Ref: K. C. Hsieh, P. R. Gray, D. Senderowicz, and D. G. Messerschmitt, “A low-noise
chopper-stabilized differential switched-capacitor filtering technique,” IEEE Journal of
Solid-State Circuits, vol. 16, issue 6, pp. 708-715, 1981.
– 47 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Chopper Stabilization
|Vi|2
Vn2
Vi
A
0
B
A1
A2
Vo
fC
f
fC
f
fC
f
fC
f
SN(f)
fC
1
-1
0
2
|VA|
Also eliminates DC offset
voltage of A1
0
2
|VB|
0
– 48 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Chopper-Stabilized Differential Op-Amp
Ф
Vi+
Ф
Ф
Ф
Vo+
Vo-
Vi-
Ф
Ф
Ф
Ф
•
Integrators/amplifiers can be built using these op-amps
•
Some oversampling is useful to facilitate the implementation
– 49 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Ideal SC Amplifier
Ф1
C2
Ф1
C1
Vi
Ф2
X
∞
Vo
A CL =
C1
C2
•
Closed-loop gain is determined by the capacitor ratio by design
•
But this is assuming X is an ideal summing node (the op-amp is ideal)
– 50 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Finite-Gain Effect in SC Amplifier
Ф1
C2
A CL =
C1
Ф1
Vi
A
X
Ф2
Vo
Q φ = V φ - V φ C
1
i
1
x
1
1
+ 0 C2
Vx φ1 = Vo φ1 = -Vx φ1 A
Q φ = -V φ C
2
x
2
1
+ Vo φ 2 - Vx φ 2 C2
Vo φ 2 = -Vx φ 2 A
Q φ = Q φ
1
Vo C1
C C + C2
1
=
≈ 1 1- 1
Vi C2 1+ C1 + C 2 C2
C2 A
C2 A
2
⇒ Vi C1 = -Vx C1 + Vo - Vx C 2
Vo = -Vx A
– 51 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Practical Issues
– 52 –
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Analog vs. Digital Supply Lines
ΔVL = L
VA = VDD - ΔVL - ΔVR
did
dt
ΔVR = idR
id=
Pad
VDD
Analog
circuits
CBP
Digital
circuits
Pad
Sharing sensitive analog supplies with digital ones is a very bad idea.
– 53 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Analog vs. Digital Supply Lines
id=
Pad
Pad
VDD
Analog
circuits
CBP
Digital
circuits
Pad
Pad
– 54 –
•
Dedicated pads
for analog and
digital supplies
•
On-chip bypass
capacitors help
(watch ringing)
•
Off-chip chokes
(large inductors)
can stop noise
propagation at
board level
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
“Supply” Capacitance
C2
…
VDD
Cp
M5
ΔVo = ΔV
M7
Cgs
Ф1
C1
M1
Ф1
C2
S
Ф2
Vi
Ф2
Cstray
M2
Vo
X
Cgd
M3
CC
Y
M4
M6
VSS
•
Any summing-node stray capacitance can be a potential coupling path.
•
VDD, VSS, substrate, clock line, and digital noises, body effect, etc.
•
Fully differential circuits help to reject common-mode noise and coupling.
– 55 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
“Supply” Capacitance
C2
Cbot
p+
p well
n substrate
•
Avoid connecting bottom-plate parasitics to the summing node
•
Avoid crossing other signal lines with the summing node
•
Shielding can mitigate substrate noise coupling
– 56 –
Data Converters
EECT 7327
Switched-Capacitor Circuits
Professor Y. Chiu
Fall 2014
Clock Generation
Ф2
CLK
Ф1
Ф2
Ф1
•
Clock-gated ring structure
•
Non-overlapping time determined by inverter delays, sensitive to process,
voltage, and temperature (PVT) variations
•
DLL is an alternative, often used in high-speed designs
– 57 –