Transcript Chapter #7: Sequential Logic Case Studies
Introduction
Chapter #7: Sequential Logic Case Studies
10-1
Motivation
• Flipflops: most primitive "packaged" sequential circuits
Introduction • More complex sequential building blocks:
Storage registers, Shift registers, Counters Available as components in the TTL Catalog • How to represent and design simple sequential circuits: counters
• Problems and pitfalls when working with counters:
Start-up States Asynchronous vs. Synchronous logic 10-2
Chapter Overview
Introduction Examine Real Sequential Logic Circuits Available as Components
• Registers for storage and shifting • Random Access Memories • Counters
Counter Design Procedure
• Simple but useful finite state machine • State Diagram, State Transition Table, Next State Functions • Excitation Tables for implementation with alternative flipflop types
Synchronous vs. Asynchronous Counters
• Ripple vs. Synchronous Counters • Asynchronous vs. Synchronous Clears and Loads 10-3
Kinds of Registers and Counters
Storage Register
Group of storage elements read/written as a unit + Clr
Introduction
4-bit register constructed from 4 D FFs Shared clock and clear lines D3 Q3 S R
Schematic Shape
D2 D1 Q2 Q1 171
12 13 CLK CLR 11 5 4 14 D3 D2 D1 D0 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 9 10 7 6 3 2 1 15
D0 Clk Q0 TTL 74171 Quad D-type FF with Clear (Small numbers represent pin #s on package) 10-4
Kinds of Registers and Counters
Input/Output Variations
Selective Load Capability Tri-state or Open Collector Outputs True and Complementary Outputs 377
11 1 18 17 14 13 8 7 4 3 CLK EN D7 D6 D5 D4 D3 D2 D1 D0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 9 6 5 2 19 16 15 12
74377 Octal D-type FFs with input enable
EN enabled low and lo-to-hi clock transition to load new data into register Introduction
11 18 17 14 13 8 7 4 3
374
H G F E D CLK QH QG QF QE QD C B A QC QB QA OE 1 19 16 15 12 9 6 5 2
74374 Octal D-type FFs with output enable
OE asserted low presents FF state to output pins; otherwise high impedence
10-5
Kinds of Registers and Counters
Register Files
Two dimensional array of flipflops Address used as index to a particular word Word contents read or written
11 4 12 5 13 14 RE RB RA WE WB WA
670
3 2 1 15 D4 D3 D2 D1 Q4 Q3 Q2 Q1 6 7 9 10
74670 4x4 Register File with Tri-state Outputs
Introduction
Separate Read and Write Enables Separate Read and Write Address Data Input, Q Outputs Contains 16 D-ffs, organized as four rows (words) of four elements (bits) 10-6
Kinds of Registers and Counters
Shift Registers Introduction
Shift \Reset
CLK
Storage + ability to circulate data among storage elements +
CLK
Shift Direction
CLK CLK
\Reset
Shif t Shif t Shif t Q 1 1 0 0 0 Q 2 0 1 0 0 Q 3 0 0 1 0 Q 4 0 0 0 1
+ Shift from left storage element to right neighbor on every lo-to-hi transition on shift signal Wrap around from rightmost element to leftmost element
Master Slave FFs: sample inputs while clock is high; change outputs on falling edge
10-7
Kinds of Registers and Counters
Shift Register I/O
Serial vs. Parallel Inputs Serial vs. Parallel Outputs Shift Direction: Left vs. Right
10 9 7 6 5 4 3 C B A S1 S0 LSI D 2 11 1 RSI CLK CLR 194 QD 12 QC 13 QB 14 QA 15
74194 4-bit Universal Shift Register Serial Inputs: LSI, RSI Parallel Inputs: D, C, B, A Parallel Outputs: QD, QC, QB, QA Clear Signal Positive Edge Triggered Devices
S1,S0 determine the shift function
S1 = 1, S0 = 1: Load on rising clk edge synchronous load S1 = 1, S0 = 0: shift left on rising clk edge LSI replaces element D S1 = 0, S0 = 1: shift right on rising clk edge RSI replaces element A S1 = 0, S0 = 0: hold state
Introduction
Multiplexing logic on input to each FF!
Shifters well suited for serial-to-parallel conversions, such as terminal to computer communications 10-8
Kinds of Registers and Counters
Shift Register Application: Parallel to Serial Conversion
D7 D6 D5 D4 Parallel Inputs Clock
10 9 7 6 5 4 3 2 11 1 S1 S0 LSI D C B A RSI CLK CLR 194 QD QC QB QA 10 9 7 6 5 4 3 2 11 1 S1 S0 LSI D C B A RSI CLK CLR 194 QD QC QB QA
D7 D6 D5 D4
Introduction
Parallel Outputs D3 D2 D1 D0
10 9 7 6 5 4 3 2 11 1 S1 S0 LSI D C B A RSI CLK CLR 194 QD QC QB QA 10 9 7 6 5 4 3 2 11 1 S1 S0 LSI D C B A RSI CLK CLR 194 QD QC QB QA
D3 D2 D1 D0 Serial transmission 10-9
Kinds of Registers and Counters
Introduction Counters
Proceed through a well-defined sequence of states in response to count signal 3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...
3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...
Gray Code Counter : 000, 001, 011, 010, 110, 100, 101, 111, ...
Binary vs. BCD vs. Gray Code Counters A counter is a "degenerate" finite state machine/sequential circuit where the state is the only output 10-10
Kinds of Registers and Counters Ring Counter + \Reset Shift Direction Shift J
CLK
Q K /Q
CLK CLK CLK
+ 1000, 0100, 0010, 0001, 1000, ...
\Reset
Introduction
10-11
Kinds of Registers and Counters
Johnson (Mobius) Counter
+ + +
Introduction
1 0 \Res et J S Q CLK K R Q Q 1 J S Q CLK K R Q Q 2 J S Q CLK K R Q Q 3 J S Q CLK K R Q Q 4
End-Around
Shif t + 100 Shif t Q 1 Q 2 Q 3 Q 4 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0
8 possible states, single bit change per state, useful for avoiding glitches 10-12
Kinds of Registers and Counters
Catalog Counter
7 10 2 6 5 4 3 D C B A P T
163
CLK RCO 15 QD QC QB QA 11 12 13 14 9 1 LOAD CLR
74163 Synchronous 4-Bit Upcounter
Introduction
Synchronous Load and Clear Inputs Positive Edge Triggered FFs Parallel Load Data from D, C, B, A P, T Enable Inputs: both must be asserted to enable counting RCO: asserted when counter enters its highest state 1111, used for cascading counters
"Ripple Carry Output"
74161: similar in function, asynchronous load and reset 10-13
P T D CLK Q A Q B Q C Q D RCO CLR LOAD A B C
Kinds of Registers and Counters
74163 Detailed Timing Diagram
Clear 12 Load 13 14 15 Count 0 1 2 Inhibit
Introduction
10-14
000 001 010 011
Counter Design Procedure
Introduction Introduction
This procedure can be generalized to implement ANY finite state machine Counters are a very simple way to start: no decisions on what state to advance to next current state is the output Example: 3-bit Binary Upcounter
111
Present State Next State Flipflop Inputs
11 0 101 100 State Transition Digram
State Transition Table Flipflop Input Table
Decide to implement with Toggle Flipflops
What inputs must be presented to the T FFs to get them to change to the desired state bit?
This is called "Remapping the Next State Function" 10-15
000 001 010 011
Counter Design Procedure
Introduction Introduction
This procedure can be generalized to implement ANY finite state machine Counters are a very simple way to start: no decisions on what state to advance to next current state is the output Example: 3-bit Binary Upcounter
111
Present State Next State Flipflop Inputs
11 0 101 100 State Transition Digram
State Transition Table Flipflop Input Table
Decide to implement with Toggle Flipflops
What inputs must be presented to the T FFs to get them to change to the desired state bit?
This is called "Remapping the Next State Function" 10-16
K-maps for Toggle Inputs: A CB 00 0 1
Counter Design Procedure
Example Continued
Resulting Logic Circuit: 01 11 10 TA = A CB 00 0 01 11 10 1 TB = A CB 00 0 01 1 11 10 TC =
Introduction
10-17
K-maps for Toggle
0
Counter Design Procedure
Example Continued
A CB 00 1
Inputs:
01 1 11 1 C 10 1
Resulting Logic Circuit:
+ 1 1 1 B T A = 1 1 1 T S Q CLK R Q QA T S Q CLK Q R QB \Reset A CB 00 0 0 01 0 11 C 10 0 0 Count
Timing Diagram:
1 1 1 1 1 B TB = A A CB 00 0 0 01 0 11 0 C 10 0 1 0 1 1 0 \Res et Q C Q B Q A Count B TC = A • B
Introduction
T S Q QC CLK Q R 100
10-18
Counter Design Procedure
More Complex Count Sequence
Step 1: Derive the State Transition Diagram Count sequence: 000, 010, 011, 101, 110 Present State Next State
Introduction
Step 2: State Transition Table 10-19
Counter Design Procedure
More Complex Count Sequence
Step 1: Derive the State Transition Diagram Count sequence: 000, 010, 011, 101, 110 Present State Next State
Introduction
Step 2: State Transition Table Note the Don't Care conditions 10-20
Counter Design Procedure
More Complex Count Sequence
Step 3: K-Maps for Next State Functions A CB 00 0 01 1 11 10 C+ = A CB 00 0 01 1 11 10 A+ = A CB 00 0 01 1 11 10 B+ =
Introduction
10-21
Counter Design Procedure
More Complex Count Sequence
Step 3: K-Maps for Next State Functions A CB 00 0 0 1 X 01 0 1 C 11 0 10 X X 1 C+ A CB 00 0 1 1 X 01 1 0 C 11 0 10 X X 1 B+
Introduction
B B A CB 00 0 0 1 X 01 1 1 C 11 0 10 X X 0 A+ B 10-22
Counter Design Procedure
More Complex Counter Sequencing
Step 4: Choose Flipflop Type for Implementation Use Excitation Table to Remap Next State Functions Present State Toggle Inputs
Introduction Toggle Excitation Table Remapped Next State Functions
10-23
Counter Design Procedure
More Complex Counter Sequencing
Step 4: Choose Flipflop Type for Implementation Use Excitation Table to Remap Next State Functions Present State Toggle Inputs
Introduction Toggle Excitation Table Remapped Next State Functions
10-24
Counter Design Procedure
More Complex CounterSequencing
Remapped K-Maps A CB 00 0 01 11 10 1 TC A CB 00 0 01 1 11 10 TB
Introduction
A CB 00 0 01 1 11 10 TA TC = TB = TA = 10-25
Counter Design Procedure
More Complex CounterSequencing
Remapped K-Maps C A CB 00 01 11 10 0 0 0 1 X 1 X 1 X 0 TC B A 0 CB 00 0 1 X 01 1 0 11 0 X C 10 X 1 B TC = A C + A C = A xor C TB = A + B + C TA = A B C + B C
Introduction
A 0 CB 00 1 1 X 01 0 1 11 1 X C 10 X 1 TB B 10-26
Counter Design Procedure
More Complex Counter Sequencing Introduction
Resulting Logic: 5 Gates 13 Input Literals + Flipflop connections Count A C A /B C
TC T S Q C CLK Q R \C TB
TC TB /A B /C /B C
T S Q B CLK R Q \B TA T S Q A CLK Q R \A
0 \Reset 1 TA Timing Waveform:
100 Count \Res et C B A 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 1 1 0 0 0 0
10-27
Self-Starting Counters
Start-Up States
At power-up, counter may be in possible state
Introduction
Designer must guarantee that it (eventually) enters a valid state Especially a problem for counters that validly use a subset of states
Self-Starting Solution:
Design counter so that even the invalid states eventually transition to valid state
111 111 000 110 000 110
Implementation in Previous Slide!
010 101 010 101 001 011 100 001 011 100 Two Self-Starting State Transition Diagrams for the Example Counter
10-28
A 0 CB 00 1 1
Self-Starting Counters
Deriving State Transition Table from Don't Care Assignment Introduction
A 0 1
Input to Toggle Flip-Flops c
CB 00 01 11 10 0 0 1 1 TC A 0 CB 00 0 1 1 0 0 1 1
State Changes
01 0 1 11 0 1
c
10 0 1 1 01 0 1 B 11 1 1
c
10 1 1 TB A 0 CB 00 1 1 1 B 01 1 0 11 0 0
c
10 1 1 C+ B+ State Transition Table Present State C 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 Next State C+ 0 1 0 1 0 1 0 1 B+ 1 1 1 0 1 1 0 0 A+ 0 1 1 1 1 0 0 1 B A 0 CB 00 0 1 0 01 1 0 11 0 0
c
10 1 1 TA B A 0 CB 00 0 1 1 01 1 1 11 0 1
c
10 1 0 A+ B B 10-29
Introduction
Self-Srarting Counters Counter Reset Usual to have a distinguished starting state for the counter or finite state machine Desirable to include additional hardware to reset the counter to this state Use reset signal to place flipflops in the desired starting state 10-30
Implementation with Different Kinds of FFs
Introduction
Toggle - natural D - compatible with CAD software such as espresso JK - fewest gates in usual As the level of integration continues to increase saving a gate here or there becomes less of an use 10-31
Implementation with Different Kinds of FFs
R-S Flipflops Introduction
Continuing with the 000, 010, 011, 101, 110, 000, ... counter example Present State Next State Remapped Next State
Q+ = S + R Q
RS Exitation Table Remapped Next State Functions 10-32
Implementation with Different Kinds of FFs
RS FFs Continued
A CB 00 0 01 1 11 10 A CB 00 0 01 1 11 10 RC A CB 00 0 01 11 1 RB 10 SC A CB 00 0 01 11 10 1 SB A CB 00 0 01 1 11 10 RA A CB 00 0 01 1 11 10 SA RC = SC = RB = SB = RA = SA =
Introduction
10-33
Implementation with Different Kinds of FFs
RS FFs Continued
A 0 CB 00 X 1 X 01 X 0 11 1 X C 10 X 0
RC
A 0 CB 00 0 1 X 01 0 1 B 11 1 X C 10 X 0
RB
A 0 CB 00 X 1 X 01 0 0 B 11 X X C 10 X 1
RA
B A 0 CB 00 0 1 X 01 0 1 11 0 X C 10 X X
SC
A 0 CB 00 1 1 X 01 X 0 B A 0 CB 00 0 1 X 01 1 X B 11 0 X B 11 0 X C 10 X 1 C 10 X 0
SB SA Introduction
RC = A SC = A RB = A B + B C SB = B RA = C SA = B C 10-34
Implementation With Different Kinds of FFs
RS FFs Continued Introduction
\ A A R Q CLK S Q C \ C RB \ B R Q B CLK S Q \ B C SA A R Q CLK S Q \A Count A C B RB B \C
Resulting Logic Level Implementation: 3 Gates, 11 Input Literals + Flipflop connections
SA
10-35
Implementation with Different FF Types
J-K FFs
Present State Next State
Introduction
Remapped Next State
Q+ = J Q + K Q
J-K Excitation Table Remapped Next State Functions 10-36
Implementation with Different FF Types
J-K FFs Continued
A CB 00 0 01 1 11 10 A CB 00 0 01 1 11 10 JC A CB 00 0 01 11 1 JB 10 KC A CB 00 0 01 11 10 1 KB A CB 00 0 01 1 11 10 JA A CB 00 0 01 1 11 10 KA JC = KC = JB = KB = JA = KA =
Introduction
10-37
Implementation with Different FF Types
J-K FFs Continued
A 0 CB 00 0 1 X 01 0 1 11 X X C 10 X X
JC
A 0 CB 00 1 1 X 01 X X B 11 X X C 10 X 1
JB
A 0 CB 00 0 1 X 01 1 X B 11 0 X C 10 X X
JA
B A 0 CB 00 X 1 X 01 X X 11 1 X C 10 X 0
KC
A 0 CB 00 X 1 X 01 0 1 B A 0 CB 00 X 1 X 01 X 0 B 11 X X B 11 1 X C 10 X X C 10 X 1
KB KA Introduction
JC = A KC = A JB = 1 KB = A + C JA = B C KA = C 10-38
Implementation with Different FF Types
J-K FFs Continued
+
Introduction
Count A \ A J Q CLK K Q C \ C KB J Q CLK K Q B \ B JA C J Q CLK K Q A \ A A C KB B \ C JA
Resulting Logic Level Implementation: 2 Gates, 10 Input Literals + Flipflop Connections 10-39
Implementation with Different FF Types
D FFs
Simplest Design Procedure: No remapping needed!
DC = A DB = A C + B DA = B C
A D Q C CLK Q \ C DB D Q B CLK Q \ B DA D Q A CLK Q \ A Count
Introduction
\ C \ A DB B \ C \ B
Resulting Logic Level Implementation: 3 Gates, 8 Input Literals + Flipflop connections
DA
10-40
Implementation with Different FF Types
Comparison
• T FFs well suited for straightforward binary counters But yielded worst gate and literal count for this example!
Introduction
• No reason to choose R-S over J-K FFs: it is a proper subset of J-K R-S FFs don't really exist anyway J-K FFs yielded lowest gate count Tend to yield best choice for packaged logic where gate count is key • D FFs yield simplest design procedure Best literal count D storage devices very transistor efficient in VLSI Best choice where area/literal count is the key 10-41
Asynchronous vs. Synchronous Counters
Ripple Counters Introduction
Deceptively attractive alternative to synchronous design style Count signal ripples from left to right State transitions are not sharp!
Can lead to "spiked outputs" from combinational logic decoding the counter's state 10-42
Asynchronous vs. Synchronous Counters
Cascaded Synchronous Counters with Ripple Carry Outputs Introduction First stage RCO enables second stage for counting
RCO asserted soon after stage enters state 1111 also a function of the T Enable Downstream stages lag in their 1111 to 0000 transitions Affects Count period and decoding logic 10-43
Asynchronous vs. Synchronous Counters
Introduction The Power of Synchronous Clear and Load
Starting Offset Counters: e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110, ...
100 D C B A
1 6 3
P T R C O C L K Q D Q C Q Q B A D C B A L O A D C L R Cloc k Load D C B A + + Load 0 1
0110 is the state to be loaded
Use RCO signal to trigger Load of a new state Since 74163 Load is synchronous, state changes only on the next rising clock edge 10-44
Asynchronous vs. Synchronous Counters
Offset Counters Continued
Ending Offset Counter: e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000
CLR
Introduction
D C B A
1 6 3
P T R C O C L K Q Q Q Q D C B A D C B A L O A D C L R
+
Decode state to determine when to reset to 0000
1 0
Clear signal takes effect on the rising count edge Replace '163 with '161, Counter with Async Clear Clear takes effect immediately!
10-45
Random Access Memories
Static RAM Introduction
Transistor efficient methods for implementing storage elements Small RAM: 256 words by 4-bit Large RAM: 4 million words by 1-bit We will discuss a 1024 x 4 organization use MOS small # easy to implement Data j Data j Word Enable i Words = Rows Static RAM Cell Static RAM Cell Static RAM Cell Columns = Bits (Double Rail Encoded) 10-46
Random Access Memories
Static RAM Organization
Chip Select Line (active lo) Write Enable Line (active lo) 10 Address Lines 4 Bidirectional Data Lines
10 24 x 4 SRAM A5 A4 A3 A2 A1 A0 CS WE A9 A8 A7 A6 IO3 IO2 IO1 IO0
Introduction
10-47
Random Access Memories
RAM Organization Introduction
Long thin layouts are not the best organization for a RAM Some Addr bits select row A9 A8 A7 A6 A5 A4 Address Buffers Row Decoders 64 x 16 64 x 16 64 x 16 64 x 16 64 x 64 Square Array Some Addr bits select within row A3 A2 A1 A0 CS WE Address Buffers Column Decoders Sense Amplifiers Data Buffers Amplifers & Mux/Demux I/O0 I/O1 I/O2 I/O3 10-48
Random Access Memories
RAM Timing
WE
Simplified Read Timing
CS Address Data Out WE
Simplified Write Timing
CS Address Data In Data Out
Introduction
Memory Cy cle T ime V alid Address Input Dat a
10-49
Random Access Memories
Dynamic RAMs
Word Line Bit Line
Introduction
1 Transistor (+ capacitor) memory element Read: Assert Word Line, Sense Bit Line Write: Drive Bit Line, Assert Word Line Destructive Read-Out Need for Refresh Cycles: storage decay in ms Internal circuits read word and write back 10-50
Random Access Memories
DRAM Organization Introduction
Long rows to simplify refresh Two new signals: RAS, CAS Row Address Strobe Column Address Strobe replace Chip Select Row Decoders Storage Matrix 64 x 64 Row Address A11 . . .
A0 RAS CAS WE Control Logic Column Address & Control Signals Column Latches, Multiplexers/Demultiplexers DOUT DIN 10-51
Random Access Memory
RAS, CAS Addressing
Even to read 1 bit, an entire 64-bit row is read!
Introduction
Separate addressing into two cycles: Row Address, Column Address Saves on package pins, speeds RAM access for sequential bits!
Read Cycle Address RAS CAS Dout Read Row Row Address Latched Row Address Read Bit Within Row Column Address Latched Col Address Valid Tri-state Outputs 10-52
Random Access Memory
Write Cycle Timing
(1) Latch Row Address Read Row (2) WE low Address RAS CAS WE Din (3) CAS low: replace data bit Row Address Col Address Valid
Introduction
(4) RAS high: write back the modified row (5) CAS high to complete the memory cycle 10-53
Random Access Memory
RAM Refresh Introduction
Refresh Frequency: 4096 word RAM -- refresh each word once every 4 ms Assume 120ns memory access cycle 4ms
40
This is one refresh cycle every 976 ns (1 in 8 DRAM accesses)!
But RAM is really organized into 64 rows
ns x 64 This is one refresh cycle every 62.5
m
s (1 in 500 DRAM accesses) Large capacity DRAMs have 256 rows, refresh once every 8
m
s 512 rows, refresh once every 16
m
s RAS-only Refresh (RAS cycling, no CAS cycling)
2.5
x 4 External controller remembers last refreshed row 250
m
s 500
m
s Some memory chips maintain refresh row pointer CAS before RAS refresh: if CAS goes low before RAS, then refresh 10-54
Random Access Memory
DRAM Variations
Page Mode DRAM:
Introduction
read/write bit within last accessed row without RAS cycle RAS, CAS, CAS, . . ., CAS, RAS, CAS, ...
New column address for each CAS cycle Static Column DRAM: like page mode, except address bit changes signal new cycles rather than CAS cycling on writes, deselect chip or CAS while address lines are changing Nibble Mode DRAM: like page mode, except that CAS cycling implies next column address in sequence -- no need to specify column address after first CAS Works for 4 bits at a time (hence "nibble") RAS, CAS, CAS, CAS, CAS, RAS, CAS, CAS, CAS, CAS, . . .
10-55
Random Access Memory
Introduction Detailed SRAM Timing
Read Cycle Access time : takes for an address change to cause new data to appear at the output Cycle time : between the start of one read operation and a subsequent read SRAM : access time = cycle time SRAM : access time < cycle time 10-56
Chapter Summary
Introduction
# The Variety of Sequential Circuit Packages Registers, Shifters, Counters, RAMs # Counters as Simple Finite State Machines # Counter Design Procedure 1. Derive State Diagram 2. Derive State Transition Table 3. Determine Next State Functions 4. Remap Next State Functions for Target FF Types Using Excitation Tables; Implement Logic # Different FF Types in Counters J-K best for reducing gate count in packaged logic D is easiest design plus best for reducing wiring and area in VLSI # Asynchronous vs. Synchronous Counters Avoid Ripple Counters! State transitions are not sharp Beware of potential problems when cascading synchronous counters Offset counters: easy to design with synchronous load and clear Never use counters with asynchronous clear for this kind of application 10-57