Transcript Lithography
Background
Process steps up to ‘creating the transistors’ in the manufacturing Line==> Front End Of Line ==> FEOL Connecting the Transistors, capacitors etc ==> BEOL Semiconductor Band Structure, current carriers, mobility, bias MOS device basics structure, Operation, depletion, inversion, pinch off Issues Steps in manufacturing 4/26/2020 2
N
FEOL: Device
BiPolar Device- Schematic
+ P N N P N Emitter Base Collector Forward Bias + N P N Reverse Bias + + -
FEOL: FET Device - Simplified Schematic
Gate (Base) Source (Emitter) P Gate Dielectric (oxide) P P N-Well Drain (Collector) Electric Field of gate PMOS NMOS is similar (swap P and N)
Background: Electron Bands
Electrons in an atom can hold only certain energy levels (allowed levels, quantized energy levels) Solution of Schroedinger’s equation When two identical atoms come close (eg. Silicon and silicon), electron levels split Pauli’s exclusion principle for fermions almost always valid (* neutron stars, black holes ) “bands” When many atoms come together, allowed energy levels form Electrons temporal/spatial position given by wave function (uncertainity principle)
Allowed Energy Levels
Background: Bands
1 Atom N Atom Allowed Energy Levels When many atoms come together, the energy bands form
Background: Bands
Energy bands and gaps depend on space between the atoms Energy Space between atoms
Background: Solid groups
Solids: Ionic bond, covalent bond, metallic bond insulator, metal, semiconductor Resistivity insulator: > 1Mohm-cm conductor: < 10 uohm-cm at room temperature
Background: Band gap
Energy bands and gaps depend on space between the atoms METAL INSULATOR Filled levels Empty levels Energy BAND GAP Space between atoms Space between atoms
Background: Bandgap
Semi conductors similar to insulators with small band gap ( 1eV) (Insulators > 3eV) Valence band : Top most occupied band Conduction band: lowest empty band Valence and conduction bands overlap: Metal Band gap: D E between top of valence band and bottom of conduction band Metals: Band overlap
Background: Resistance vs Temp
Indirect and Direct Band Gap Silicon - indirect, GaAs- Direct band gap phonon assisted jump (momentum, energy) Resistance vs Temp phonon scattering: metal: electron in conduction bands/ holes in valence bands: semiconductor
Background: Semiconductors
Silicon is “ intrinsic ” semiconductor Addition of other ‘contaminant’ (Dopant) to alter its conductivity : Extrinsic N Type (negative) or P Type (positive) Donor electron, Acceptor hole (larger effective mass) Phosphorous for N Type, Boron for P Type (for example) of protons = number of electrons) B IIIA 13 5 C IVA 14 6 N VA 15 7 VIA O 16 8 Counter doping (when some P and some N type materials are added) ( junction is where N = P) Al Si P S In 31 32 33 Sn Sb Te 34 Ga Ge As 49 50 51 Se 52
Background: Conduction
For intrinsic semiconductors (based on calculations)
n
N c
exp
E C kT
E F
p
N V
exp
E F kT
E V
E F - Fermi level. Energy where the prob(electron) = 0.5
= half way between E C and E V for semiconductor
np
V
exp
E C kT
E V
For intrinsic case, n = p
V
E g kT
Background: Doping
N Atom Allowed Energy Levels E F Conduction Valence N Doping P Doping Dopant Valence Band Doping shifts Fermi level, smaller “band gap” Extrinsic Semiconductor : “n” not equal to “p”
Background: Doping
Majority carrier, Minority carrier Carrier Mobility hole has heavier (effective) mass less mobile P-N junction depletion region PN junction E C E F E V N Type P Type E F E F N P
Background: Bias
Reverse Bias and Forward Bias N connected with -ve, P with +ve : Forward Bias Opposite polarity : Reverse Bias increase in depletion region I-V curve I Reverse Forward
-
MOS CAPACITOR
+ Oxide - N - + + + + P + - P - + - P - Accumulation Depletion Inversion Mobile electrons Simple Capacitor Oxide + depletion two capacitors in series at the oxide interface.
Immobile -ve ions in the solid Similar results if the ‘top’ N is replaced by metal Originally metal was used M etal O xide S emiconductor structure or MOS structure
MOS FET
Transistor using Electric Field to control F ield E ffect T ransistor or FET Made with MOS ==> MOSFET Other types: JFET (Junction FET), MESFET etc Drain (Collector) + N-MOSFET (NMOS in short) Gate (Base) N+ Source (Emitter) N+ N+ P
MOS FET: Structure
NMOS: By definition, Source is at lower voltage than drain PMOS: By definition, Source is at higher voltage than drain NMOS: I DS PMOS: I DS (Drain to Source current) is positive is negative NMOS Gate (Base) Drain (Collector) + N+ Source (Emitter) N+ N+ P
NMOS: Operation
Negative gate voltage: Accumulation of holes in P region, near oxide No formation of Channel NMOS Gate (Base) Drain (Collector) + N+ + + + + P N+ Source (Emitter)
NMOS: Operation
Positive gate voltage: Depletion of holes near the oxide No channel formation Drain (Collector) + N+ NMOS Gate (Base) N+ + P N+ Source (Emitter)
NMOS: Operation
MORE positive gate voltage Inversion: Accumulation of electrons in P region (minority carrier is more than the majority carrier) near oxide Formation of Channel NMOS Gate (Base) Drain (Collector) + Source (Emitter) N+ N+ + + + + - - - P N+ Trapped charges in gate ==> Flash memory
NMOS: Operation
Threshold Voltage V T , Gate Voltage V G and Drain Voltage V D .
If Source is grounded, then V DS , Source Voltage V is same as V D S Drain (Collector) + N+ NMOS inversion Gate (Base) N+ + + + + - - - P N+ Source (Emitter)
NFET Behavior
For V G > V T , Channel forms (V G - V T ) is the
overdrive
Small shifts in VG causes large changes in I DS V T depends on Doping in P and oxide thickness I DS depends on V G and V DS Analogy: Water flow (from MIT EE web site) Source and Drains are two tanks, Channel is pipe connecting two tanks and Gate is the valve V DS is the height difference between source and drain tanks V G indicates the position of valve Opening the valve more increases flow (electron concentration) Increasing the height difference increases the flow (field)
NFET Behavior
Beyond a limit, increase in height V DS changes the behavior No more increase in current flow (for a given V G )
NFET I-V curve
When V DS is very large (> V G -V T ) LINEAR I DS V G -V T =0.6 V V Saturation current T V G I DS SATURATION V G -V T =0.4 V V G - V T = 0.2V
V G = V T CUT OFF V DS I DSAT depends on V G and on the gate length (channel length)
Drain (Collector) +
NMOS: Operation
NMOS Gate (Base) N+ N+ + + + + - - - P N+ Source (Emitter) NOTE: Inversion layer will be thicker near source and thinner near drain
Drain (Collector) +
NMOS: Pinch Off
NMOS Gate (Base) N+ N+ + + + + - - - P N+ Source (Emitter) When V DS is very high (= V G -V T ), Inversion layer thickness becomes zero near drain Pinch off However, no barrier to current flow
NMOS: Beyond Pinch Off
NMOS Gate (Base) Drain (Collector) + Source (Emitter) N+ N+ + + + + - - - P N+ Beyond pinch off, increasing V increase in I D DS does not cause increase in I D However, channel length becomes shorter and there is slight
MOSFET: Some issues
Above conclusions based on V S =0 (grounded) Otherwise, V G refers to V GS When the field is high, electrons have high energy can damage the silicon/ oxide (gate) interface near drain Hot Carrier Effect Gate (Base) Drain (Collector) + N+ + + + + Source (Emitter) - - - N+ N+ P Reduce the doping concentration near Drain Lightly Doped Drain (LDD)
MOSFET: Some issues
When channel is very short (gate length is short), depletion regions in source and drain may merge short channel effect increase doping to keep V T non zero Refer to Device books for details of the above and other issues
MOSFET: Speed
The time it takes to switch a transistor ON / OFF decides the speed of a digital circuit shorter Gate length ==> Faster switching ON/OFF Drain (Collector) + N+ Gate (Base) N+ + + + + - - - P N+ Source (Emitter)
MOSFET: Device
If the base is also lightly doped N, it is depletion mode device (ON by default). Current schematic is Enhancement mode device (OFF by default). Most devices are Enhancement mode devices Depletion devices in imperfect crystals (historical) Drain (Collector) + N+ Gate (Base) N+ + + + + - - - P N+ Source (Emitter)
FEOL: MOSFET
Combination of PMOS and NMOS is called “ C omplementary MOS” or CMOS When a voltage is applied to the gates, one transistor is on and the other is off
CMOS - Advantages
Scalable Power consumption is low Any any point of time, one of the devices is “off”