Transcript HPTDC talk at LECC2003 (Amsterdam)

A 20 ps TDC readout module
for the Alice Time of Flight system:
design and test results
P. Antonioli
INFN- Bologna
On behalf of the ALICE-TOF Group
9th Workshop on Electronics
for LHC Experiments
2 October 2003
P. Antonioli (INFN/Bologna)
Outline
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A brief overview of the ALICE-TOF detector and its
readout system
The ALICE/TOF TDC Readout Module (based on
HPTDC from CERN) conceptual design
Card prototypes results:
1.
Integral Non-Linearity effects
2.
Resolution study
3.
Test on magnetic field
4.
Test with real data
5.
Crosstalk issues
Conclusions and outlook
9th Workshop on Electronics
for LHC Experiments
2 October 2003
P. Antonioli (INFN/Bologna)
The ALICE TOF detector
Detector based on MultiGap Resistive Plate Chambers, which
can reach excellent intrinsic time resolution ( 50 ps)
MRPC detector
providing PID
information
160,000 ch
< 100 ps resolution
required
9th Workshop on Electronics
for LHC Experiments
2 October 2003
P. Antonioli (INFN/Bologna)
Readout scheme
ONE TOF SECTOR
Modules
Cable route
TRMs
DRM + LTM
18 TOF sectors
for a total of
160,000 ch.
FEE provides preamplification,
discrimination and
shaping realized with
a custom ASIC.
Output: LVDS
TOF readout crate
2 custom VME64x crates positioned at the end of each sector.
Each crate hosting 10 TDC card (240 ch, with 30 HPTDC on board) +
readout and trigger modules
9th Workshop on Electronics
for LHC Experiments
2 October 2003
P. Antonioli (INFN/Bologna)
TRM uses HPTDC
TRM card is based on HPTDC chip
developed at CERN by Microelectronic group.
HPTDC is capable in its Very High Resolution
Mode of 24.4 ps bin size.
HPTDC has LVDS inputs, internal buffers, multihit, multi-event and trigger matching capabilities
and it is also able to measure pulse width
(sensitive to leading and trailing edges).
In VHRM: 8 ch/chip.
Three versions of the chip released before its final
production (2003/4).
9th Workshop on Electronics
for LHC Experiments
27 mm
2 October 2003
P. Antonioli (INFN/Bologna)
HPTDC architecture
HPTDC is fed by a 40 MHz clock giving
us a basic 25 ns period (coarse count).
A PLL (Phase Locked Loop) device
inside the chip does
clock multiplication by a factor 8 (3 bits)
to 320 MHz (3.125 ns period) .
A DLL (Delay Locked Loop) done by
32 cells fed by the PLL clock acts a
5 bits hit register for each PLL clock (98
ps width LSB = 3.125 ns/32).
4 R-C delay lines divides each DLL bin
in 4 parts (R-C interpolation)
9th Workshop on Electronics
for LHC Experiments
2 October 2003
P. Antonioli (INFN/Bologna)
TRM conceptual design
INPUTS (LVDS)
HPTDC
TRG
32
x 15
L1
TRG
INPUTS (LVDS)
HPTDC
Readout
Controller
Output
Fifo
32
VME
Interface
32
32
x 15
32
L2a
L2a
L2r
L2r
SRAM
SRAM
9th Workshop on Electronics
for LHC Experiments
32
32
Event
Manager
32
DSP
2 October 2003
P. Antonioli (INFN/Bologna)
Notes on TRM architecture
 The VME bus is a robust industrial standard. Even if
currently not needed (conservative required bandwidth of
the card is 16 MB/s) firmware upgrade to 2eVME possible.
 The design is highly flexible: different readout schemes
and data processing can be applied during the life cycle of
the experiment, when needed.
 For the DSP high level tools are available, making easier
code maintenance and upgrades.
9th Workshop on Electronics
for LHC Experiments
2 October 2003
P. Antonioli (INFN/Bologna)
Integration with Trigger
HPTDC matching window (100ns)
MRPC Hits
HPTDC trigger latency = L1 latency
Hits moved to HPTDC readout FIFOs on L1
(matching)
L1
L2
6.7 ms
94.7 ms
Readout Controller move hits from readout
FIFO to TRM event buffer through Event
Manager. DSP receives and processes data.
On L2 accept, DSP transfers packed event to
Output Fifo. On L2 reject DSP discards data.
DSP provides: data packing, INL correction,
and data monitor at first level trigger
9th Workshop on Electronics
for LHC Experiments
2 October 2003
P. Antonioli (INFN/Bologna)
TRM development cards
TRG
HPTDC
32
x 15
L1
TRG
HPTDC
Readout
Controller
32
x 15
Output
Fifo
32
VME
Interface
32
32
L2r
Separate HPTDC
issues from readout
and data processing
L2a
L2r
L2r
SRAM
32
SRAM
32
9th Workshop on Electronics
for LHC Experiments
Event
Manager
32
DSP
2 October 2003
P. Antonioli (INFN/Bologna)
Integral non linearity
HPTDC
1.3:
INL stillINL
there
but effect
reduced.
HPTDC
shows
pattern
in its
high resolution modes
-Main source of INL
pattern is clock noise
from the logic part
through the power
supply
-same “pattern” of INL
observed in different
chip and channels
- values of RMS (as
estimated through INL)
between 40-60 ps
9th Workshop on Electronics
for LHC Experimentsthrough
INL compensation
look-up
2 October 2003
P.
Antoniolineeded
(INFN/Bologna)
tables
Time resolution
Time resolution tested
through delay lines.
Without
Without
INL compensation
INL compensation
AfterAfter
INL compensation
INL compensation
9th Workshop on Electronics
for LHC Experiments
Resolution after
apply INL
compensation under
control, more
channels tested
simultaneously.
Can we do better?
2 October 2003
P. Antonioli (INFN/Bologna)
Refined INL correction
Basic idea: we
known INL
compensation table
with resolution
better than +/- 1
HPTDC LSB.
What happen if we
apply a better
approximation to
INL (2 bits more
0.,0.25,0.5,0.75...)?
9th Workshop on Electronics
for LHC Experiments
2 October 2003
P. Antonioli (INFN/Bologna)
Refined INL correction (2)
1 bin INL comp. table
0.25 bin INL comp. table
9th Workshop on Electronics
for LHC Experiments
Adding two bits using
pseudo-bins of 6.1 ps
we can reach resolution
near 15 ps...
2 October 2003
P. Antonioli (INFN/Bologna)
Impact on overall resolution
s2 = s2MRPC + s2T0 + 2s2TDC + s2clock + s2clockTRM
Reference values:
MRPC
50 ps
T0
50 ps
TDC
25 ps
CLOCK
15 ps
CLTRM
10 ps
Total:
81 ps
9th Workshop on Electronics
for LHC Experiments
Contribution of each component
to the total
From board to board
Within board
With refined INL treatment
2 October 2003
P. Antonioli (INFN/Bologna)
(1.5%)
(3.5%)
(19%)
(39%)
(39%)
R-C calibration
Calibrating R-C lines we
divide 98 ps bin to
obtain 24.4 ps LSB
Expected relative
occurrency of each R-C
line: 0.25
Substantial
improvement with
HPTDC 1.3
9th Workshop on Electronics
for LHC Experiments
2 October 2003
P. Antonioli (INFN/Bologna)
TOT capability check
TOF reminder: we use leading and trailing
edges getting width to avoid amplitude
measurement for time slewing correction.
Check of minimal width detectable by
the HPTDC (leading and trailing edges)
6 ns pulse width looks safe, however small
variations between chips expected: FEA
ASIC of ALICE/TOF expected to safely
stretch pulses.
9th Workshop on Electronics
for LHC Experiments
2 October 2003
P. Antonioli (INFN/Bologna)
Test in magnetic field
Magnet to be setup for
EXOTIC experiment at
INFN Legnaro
laboratories.
HPTDC slave card tested
up to 0.5 T last 5 May
No functional problems observed;
0 errors detected
Space for an HPTDC
slave card
9th Workshop on Electronics
for LHC Experiments
INL pattern unchanged
2 October 2003
P. Antonioli (INFN/Bologna)
Test beam results
We showed with lab test
HPTDC can achieve 20 ps
resolution.
During tests beam, MRPC
real data measured with
HPTDC.
Obtained time resolutions
(and efficiencies) fully
compatible with “standard”
(measured with CAMAC
LeCroy TDCs) ones.
9th Workshop on Electronics
for LHC Experiments
2 October 2003
P. Antonioli (INFN/Bologna)
Test beam results (2)
May 2003:ASIC+HPTDC
9th Workshop on Electronics
for LHC Experiments
2 October 2003
P. Antonioli (INFN/Bologna)
Crosstalk measurements
Ch. 0
START Signal
Ch. 1-7
Noise signal
HPTDC
Ds
Cross Talk check:
Analyzing shifts of Tstart-Tstop varying Ds
Tstart-Tstop
STOP Signal
9th Workshop on Electronics
for LHC Experiments
Ch. 0-7
HPTDC
2 October 2003
P. Antonioli (INFN/Bologna)
Crosstalk measurements
Test repeated
over many
channels.
Larger measured
crosstalk at level
of 1 LSB
9th Workshop on Electronics
for LHC Experiments
2 October 2003
P. Antonioli (INFN/Bologna)
Crosstalk measurements
Due to charge sharing
between pads, there is a
distinct probability to have two
hits when particle cross near
pad boundaries.
It is also normal to observe
resolution worsening near the
boundary (lower charge
collected).
Is there a measurable
additional contribution from
HPTDC?
NO
9th Workshop on Electronics
for LHC Experiments
2 October 2003
P. Antonioli (INFN/Bologna)
Radiation tolerance
Low radiation levels
Irradiation
nextexpected
24/25atNovember
ALICE/TOF: 0.3 Gy/10 years and total
neutron fluence of 2 109 /cm2/10 years
Currently only one measurement done
by CMS at Louvain on HPTDC (1.1):
extrapolating their measurement we
can expect 1-2 SEU/day on the whole
experiment.
At INFN Legnaro Lab. we will
chacterize energy threshold for
SEU in HPTDC registers using
heavy ions.
Additional measurement with
protons possibly at Louvain next
year.
Devoted
HPTDC
test cardfor
for heavy
SIRAD facility
at Legnaro
ions
irradiation
@ SIRAD
irradiation
with heavy
ions
9th Workshop on Electronics
for LHC Experiments
2 October 2003
P. Antonioli (INFN/Bologna)
Towards final TRM layout
Key ingredients:
• FPGA: Altera ACEX with 100,000 gates
• DSP: Analog Devices Sharc ADSP-21160N:
- 0.18 mm technology
- large enough memory resources (4Mbits)
• Latch-up protection
• SEU “tolerant”
• Firmware upgrade through VME
To reduce board complexity and make easier maintenance:
• use 10 piggy-back cards hosting each 3 HPTDC + local voltage regulator
(24 ch matches FEA nr. Of channels and connector) mounted on each side;
• a central mother board for FPGA/DSP/memory etc.
9th Workshop on Electronics
for LHC Experiments
2 October 2003
P. Antonioli (INFN/Bologna)
Conclusions and outlook
• HPTDC tested and qualified for ALICE/TOF use
(20 ps resolution)
• All “building bricks” of final TRM card tested,
final TRM layout in advanced preparation
• TRM production due starting during 2004
9th Workshop on Electronics
for LHC Experiments
2 October 2003
P. Antonioli (INFN/Bologna)