Transcript Part I: Introduction

VLSI DESIGN USING VHDL
A workshop by
Dr. Junaid Ahmed Zubairi
October 2002
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Workshop Outline

Introduction to the workshop and setting targets
 Combinational and sequential logic
 Max+plusII package features and usage guide
 Hands on VHDL (Lab1)
 VHDL design units
 Designing a simple circuit and its testing (Lab2)
 Design of a sequential logic circuit (lab3)
 Design project
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Introduction and Setting
Targets
 This
workshop is not about synthesis or
place and route of VLSI
 It is not about the testing considerations
in VLSI
 It is about using VHDL for VLSI design
 Participants are expected to learn a
subset of VHDL features and use it on
max+plusII platform
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What is VHDL?

VHDL is VHSIC (Very High Speed Integrated
Circuits) Hardware Description Language
 VHDL is designed to describe the behavior of
the digital systems
 It is a design entry language
 VHDL is concurrent
 Using VHDL test benches, we can verify our
design
 VHDL integrates nicely with low level design
tools
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Why VHDL?

It is IEEE standard (1076 and 1164)
 VHDL now includes VITAL (IEEE 1076.4),
using which the timing information can be
annotated to a simulation model
 VITAL competes with SDF models of Verilog
 VHDL has hierarchical design units
 Learning VHDL and Verilog is easy;
mastering is difficult
 VHDL and Verilog are identical in functionality
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VHDL Within VLSI Design
Cycle

VLSI design starts with (not always!!)
capturing an idea on the back of an envelope
 From the specifications, one needs to
construct a behavioral description of the
circuit
 When one describes how information flows
between registers in a design, it is called RTL
(register transfer level)
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VHDL Within VLSI Design
Cycle

A structure level description defines the circuit
in terms of a collection of components
 VHDL supports behavioral, RTL and
structural descriptions, thus supporting
various levels of abstraction
 Most VHDL users prefer RTL descriptions
and use VHDL as input to the synthesis
process
 Synthesis tools then optimize and compile the
design as per specified constraints and map
to target devices as per libraries
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VHDL Within VLSI Design
Cycle
 Gate
level simulation is conducted to
verify the design; using the same test
vectors that were generated for RTL
simulation
 Finally the place and route tools are
used for layout generation and timing
closure
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Combinational Logic

Several combinational logic units are
available in VHDL for use in the designs
 A pure combinational logic circuit’s output
depends on its present input only
 Given the values of the present inputs, the
output of the circuit is determined based on
the logical function it implements
 A combinational circuit cannot store or buffer
any values for subsequent clock cycles.
Everything must be accomplished within the
same clock cycle!!
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Combinational Logic

The inputs to the combinational logic come
from values stored in memory elements (flip
flops or latches)
 These inputs may be applied with the rising
edge of the clock
 The circuit’s output is stabilized before the
falling edge of the clock
 The falling edge of the clock may be used to
capture the results into the memory elements
(or next rising edge may be used)
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Sequential Logic
 Memory
elements are modeled as finite
state machines
 These elements can be designed with
the help of the state diagrams
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Sequential Logic Example
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State Diagrams

Finite state machines are represented by
state diagrams
 A state diagram identifies all possible states
the machine can be in
 In each state, the machine may react to the
applied input in a specific way
 The output of the machine and its next state
is specified in a state table or state diagram
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Max+PlusII Software

We will be using Max+plusII Baseline
software by Altera
 This package allows us to write and compile
VHDL designs and perform RTL simulation
with waveforms
 Please download Max+plusII from
www.altera.com
 Using your hard disk volume serial number
(visible using dir/p), obtain the license.dat file
by filling out a form online and copy this file to
c:\mp2student
 Install the license using license management14
Max+plusII Software

Once the license is installed, you can use the
required VHDL entry, compilation and
simulation tools
 Open a new text file, specifying the extension
as .vhd and type the given source code into
the file
 Save the file with name entityname.vhd and
set the project to the current file
 Choose save and compile to remove any
errors
 Now we are ready to simulate the design
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Lab 1: Example VHDL code
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library ieee;
use ieee.std_logic_1164.all;
entity fulladd is
port (Cin,x,y:in std_logic;
s,Cout:out std_logic);
end fulladd;
architecture logicfunc of fulladd is
begin
s<=x xor y xor Cin;
Cout<= (x and y) or (Cin and x) or (Cin and y);
end logicfunc;
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Max+plusII Software

The student version has support for only
limited number of clock cycles, with t=1us
 In order to get more simulation clock cycles,
use the .scf file provided by UCLA teaching
assistants
 Open the convert.scf file and save it as
projectname.scf
 Import all input and output nodes into the
SCF file
 Modify the inputs as per need and choose
simulation
 After the simulation is finished, observe the
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VHDL Syntax

You may use UPPERCASE for reserved
words in VHDL and lowercase words for your
chosen names but it is not necessary
 The basic building blocks of VHDL design are
ENTITY declaration and ARCHITECTURE
body
 The VHDL file name must be the same as the
ENTITY name
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VHDL Syntax

ENTITY declaration treats the design as a
black box. It just names the inputs and
outputs as ports
 It does not specify how the circuit works
 The last entry in the port declaration is not
followed by a semicolon
 Each signal has a signal mode (IN, OUT or
BUFFER) and a signal type (BIT,
BIT_VECTOR, STD_LOGIC,
STD_LOGIC_VECTOR)
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VHDL Syntax

Std_logic and std_logic_vector are part of
IEEE library. They allow additional values ‘’(don’t care), ‘Z’ (hi-Z) and ‘X’ (indeterminate)
 In order to use IEEE values, you should use
the following statements:
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library ieee;
use ieee.std_logic_1164.all;
Do not mix BIT and STD_LOGIC in your
design file
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Architecture
 The
functional relation between the
input and output signals is described by
the architecture body
 Only one architecture body should be
bound to an entity, although many
architecture bodies can be defined
 Architecture body can be written in
many different ways
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Data Flow Style
 We
have used the concurrent
assignment statements in our sample
code:
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s<=x xor y xor Cin;
Cout<= (x and y) or (Cin and x) or (Cin and y);
 The
concurrent assignment takes place
based on the activity on RHS of the
arrow
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Structural Style
 We
can also describe our architecture
based on a list of components used and
mapping of our circuit’s signals to the
inputs and outputs of the components
 For example, we may use the full adder
designed earlier as a component in a
higher level design
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Using Components
 Begin
with the design of bottom units in
VHDL
 Save each unit in a separate VHDL file
 Design the top unit next, placing bottom
units in it as components
 Name the project as the top unit and
then compile
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Components (VHDL code)
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library ieee;
use ieee.std_logic_1164.all;
entity fulladd is
port (Cin,x,y:in std_logic;
s,Cout:out std_logic);
end fulladd;
architecture logicfunc of fulladd is
begin
s<=x xor y xor Cin;
Cout<= (x and y) or (Cin and x) or (Cin and y);
end logicfunc;
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Components (VHDL code)
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library ieee;
use ieee.std_logic_1164.all;
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entity adderfour is
 port (Cin:in std_logic;
 x3,x2,x1,x0:in std_logic;
 y3,y2,y1,y0:in std_logic;
 s3,s2,s1,s0:out std_logic;
 Cout:out std_logic);
 end adderfour;
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Components (VHDL code)
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architecture compo of adderfour is
signal c1,c2,c3:std_logic;
component fulladd
port (Cin,x,y:in std_logic;
s,Cout:out std_logic);
end component;
begin
stage0:fulladd port map (Cin,x0,y0,s0,c1);
stage1:fulladd port map (c1, x1,y1,s1,c2);
stage2:fulladd port map (c2,x2,y2,s2,c3);
stage3:fulladd port map (c3,x3,y3,s3,Cout);
end compo;
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Components

The source code shown builds a four-bit
ripple carry adder
 It uses four 1-bit full adders as components
 The structural style is just like specifying a
network with all its inputs, outputs and
intermediate wires
 All intermediate wires are declared in the
architecture body as signals
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Using Vectors

Instead of naming each wire separately, we
can group them together and give a common
name
 For example, in a 4-bit adder, we use four
inputs x3,x2,x1,x0
 We can also declare a vector called X.
 X :in std_logic_vector(3 downto 0);
 X(3), X(2), X(1), X(0) can be referred
individually
 Y:in std_logic_vector(0 to 3);
 Y(0), Y(1)..etc. can be referred
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Lab2: Design of a Simple
Circuit
 Using
Max+plusII, design a simple 4-bit
comparator that accepts two four bit
numbers and sets the result output bit to
one if they are found identical. Test your
circuit with one set of different inputs
and one set of identical inputs. Use A=B
to test for equality. For example,
 EQ <= ‘1’ when (A=B) else ‘0’;
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Clock Signal

Synchronous Sequential circuits require the
use of a clock signal
 Clock signal can be generated easily in VHDL
 As an example, look at the following code
segment:
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Clk <= not(Clk) after 10ns;
The Clk wire is assigned its opposite value
after 10ns. Thus this statement creates a
clock whose time period is 20ns with a 50%
duty cycle
 If you use convert.scf, you get a clock signal
with it. You can specify it as an input line
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Sequential Logic
 Design
of an edge triggered D flip flop
 (Demo)
 Adding
asynchronous reset to the flip
flop
 (Demo)
 How do you convert it to latch?
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Sequential (VHDL code)
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library ieee;
use ieee.std_logic_1164.all;
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entity my_ff is
 port (D,clk,reset:in std_logic; Q:out std_logic);
 end my_ff;
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Sequential (VHDL code)
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architecture synch of my_ff is
 begin
 process (clk,reset)
 begin
 if reset='1' then
 Q <='0';
 elsif clk='1' and clk'EVENT then
 Q<=D;
 end if;
 end process;
 end synch;
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Explanation

The source code shown implements a D flip
flop that is rising edge triggered and uses
asynchronous reset
 The rising edge is detected by the following
statement:
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elsif clk='1' and clk'EVENT then Q<=D;
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This statement says that if clk has a current
value of 1 and if there has been an event on
the clk line, assign Q the value of D
 Asynchronous reset is achieved by first
checking if reset has a value 1
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Behavior Modeling With
Process

In the D flip flop design, we have introduced
the 3rd type of architecture body, i.e.
sequential flow
 Sequential execution is implemented in VHDL
with process() statement.
 A process consists of a sensitivity list and a
series of statements to be executed in the
order in which they are written
 The process is called as soon as the value of
any one member of the sensitivity list is
changed
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Mini Exercise
 Modify
the D flip flop design to provide
the capability of asynchronous set
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Lab 3: Sequential Logic
 A circuit
is supposed to generate an
output of 1 when it detects two
consecutive 1’s at the input at the rising
edge of the clock
 Make the state diagram and complete
the hardware design
 VHDL design approach
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