Transcript Class03_Signal_Parameters_II

Signal and Timing Parameters II
Source Synchronous Timing – Class 3
a.k.a. Co-transmitted Clock Timing
a.k.a. Clock Forwarding.
Assignment for next class: Download HSPICE
manual from Intel Lab.
Acknowledgements: Intel Bus Boot Camp:
Howard Heck
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Contents
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 Synchronous Bus Limitations
 Source Synchronous Concept &
Advantages
 Operation
 Timing Equations
 Timing Loop Analysis
 Maximum Transfer Rate
 Beyond “Double Pumping”
 Edge Considerations
Signal Parameters & Timing Class 3
Common Clock Limitations
3
CLK
Clock
A
f max  1
Data
B
Tcycle ,min  Tdriver,max  T flight,max  Tsetup  Tskew
Tcycle,min
 Max frequency is defined by min cycle time
 Min cycle time is limited by maximum delays.
 Can we find a way to remove the dependence on
absolute delays?
Signal Parameters & Timing Class 3
Source Synchronous Signaling Concept
Strobe
A
B
Data
 The transmitting agent (A) sends the clock (“strobe”), along
with the data signal.
A central clock is not (directly) required to control data flow from
transmitter to receiver.
 Overview:
Drive the strobe and data signals with a known phase relationship.
Design the strobe and data signals to be identical in order to
preserve the phase relationship.
As long as the phase relationship can be maintained, the lines can
be arbitrarily long (limited by other effects, such as losses,
latencies, etc.).
Signal Parameters & Timing Class 3
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Source Synchronous Concept Example
 Suppose that we transmit a data signal 1 ns prior to




transmitting the strobe.
You’re given a 500 ps receiver setup requirement.
You find that the flight time for the data signal
varies between 5.5 ns and 5.7 ns.
You find that the flight time for the strobe signal
also varies between 5.5 ns and 5.7 ns, but the two
signals are not correlated.
Can we meet the setup requirement?
Signal Parameters & Timing Class 3
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Source Synchronous Advantage
 From the preceding example, it should be apparent
that source synchronous performance depends on
relative, rather than absolute delays.
True for drivers and interconnect, though we must still
meet the absolute setup/hold requirements for the
receiver.
 In real systems, the difference in delay between

signals can be made much smaller than the absolute
delays.
Therefore, with source synchronous signaling we
can expect
to achieve higher performance
to be able to use longer traces
Signal Parameters & Timing Class 3
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Transfer Rate Comparison
Synchronous
Source
Synchronous
133 MHz
400 MT/s
(533 MT/s)
Graphics
66 MHz
266 MT/s
(533 MT/s)
Memory
133 MHz
800 MT/s
FSB
Items in parentheses are in development, all others
are released in products.
Signal Parameters & Timing Class 3
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Source Synchronous Bus Operation
Driver Chip
From Core
D
D
Q
DELAY
Strobe n
n
From Core
D
P
L
L
Q
Data
Clock Distribution
Tree
Receiver Chip
To Core
System
Clock
Data
Q
D
Q
D
Strobe
n
P
L
L
Clock Distribution Tree
Signal Parameters & Timing Class 3
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Operation #2
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Driver Chip
From Core
 The timing path starts
DELAY
Q
Strobe n
n
From Core
D
P
L
L
Q
Data
Clock Distribution
Tree
Data
Receiver Chip
To Core
Q
D
Q
D
System
Clock
n
Strobe
at the flip-flop of the
transmitting agent and
ends at the flip-flop of
the receiving agent.
 The strobe signal is used
as the clock input of the
receiver flip-flop.
D
D
P
L
L
Clock Distribution Tree
 The transmitted strobe (and data) signals are generated
from the on-chip bus clock.
 Typically, the strobe is phase shifted by ½ cycle from the
data signal. Some buses do the shifting in the receiver.
Duty cycle variations will cause variation on the phase
relationship
Signal Parameters & Timing Class 3
Operation #2
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Driver Chip
From Core
DELAY
 Typically, there is
From Core
D
P
L
L
Q
Data
Clock Distribution
Tree
Data
Receiver Chip
To Core
System
Clock
Q
D
Q
D
n
P
L
L
Clock Distribution Tree
CLK
DATA
Hold Setup
Strobe n
n
one strobe signal
(or pair of signals)
per two bytes of
data signals.
 Varies by design
Signal relationships
at the transmitter
are shown below.
Setup
Q
Strobe

D
D
Hold
STROBE
Signal Parameters & Timing Class 3
Source Synchronous Operation
@ RECEIVER
STROBE/STROBE
@ DRIVER
Truman
Thmar
Tsu Th
Tsuskew
Thskew
Tvb
Tva
DATA
t
Tsuskew: flight time skew for setup
Tsumar: setup margin
Tvb: min driver phase offset (setup)
Thskew: flight time skew for hold
Thmar: hold margin
Tvb: min driver phase offset (hold)
Signal Parameters & Timing Class 3
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Source Synchronous Equations
@ RECEIVER
STROBE/STROBE
@ DRIVER
Truman
Thmar
Tsu Th
Tsuskew
Thskew
Tvb
Tva
DATA
The sum of the timings at the receiver must equal the
timing at the driver:
Tva  Th  Thskew  Thmar
Tvb  Tsu  Tsuskew  Tsumar
This implies that we must design with minimum driver
offsets:
Tva  Th  Thskew
Tvb  Tsu  Tsuskew
Signal Parameters & Timing Class 3
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Source Synchronous Equations #2
@ RECEIVER
STROBE/STROBE
@ DRIVER
Truman
Thmar
Tsu Th
Tsuskew
Thskew
Tvb
Tva
DATA
We must also satisfy the following relationship:
Tcycle ,min  Tva  Tvb
This determines our maximum transfer rate.
f max  1
Tcycle,min
Signal Parameters & Timing Class 3
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Question
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 Based on what we’ve covered in the previous
slides, what are the implications to:
The transmitter design?
The receiver design?
The interconnect design?
 Example:
Tsu = 500 ps, Th = 250 ps
The target transfer rate is 500 MT/s.
What are reasonable flight time skew targets?
Signal Parameters & Timing Class 3
Setup Timing Diagram & Loop Analysis
TBCLK
BCLK
TBCLK/4
DCLK
Tco(STB)
DRIVER STB/STB
Tco(DATA)
DRIVER
Tflight(STB)
DATA
RECEIVER STB/STB
Tflight(DATA)
RECEIVER
TBCLK
4
DATA
Tsu
Tsumar
 Tco STB   T flight STB   Tsu  Tsumar  Tco DATA  T flight DATA  0
Signal Parameters & Timing Class 3
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Setup Analysis
TBCLK
4
 Tco STB   T flight STB   Tsu  Tsumar  Tco DATA  T flight DATA  0
 For a “double pumped” bus, the difference between Tco(DATA)
and Tco(STB) is typically set to one-half of the cycle time
(TDCLK/2 = TBCLK/4) to center the strobe in the data valid
window.
Double pumped: source synchronous transfer rate is 2x the
central clock rate.
 This relationship is typically specified as Tvb (data “valid
before” strobe ), which signifies the minimum time for which
the data at the transmitter is valid prior to transmission of the
strobe.
TBCLK
 Mathematically: T







T
DATA

T
STB

vb , min
co
co
max
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 Simplify the loop equation:
 Tvb ,min  T flight STB   Tsu  Tsumar  T flight DATA  0
Signal Parameters & Timing Class 3
Setup Analysis #2
Tvb,min  Tsu  T flight STB   T flight DATA  Tsumar
 Both data & strobe propagate over the interconnect.
Goal: identical flight times.
 In reality, there will be some difference in flight
times between data and strobe.
trace length, loading, crosstalk, ISI, etc.
 Define flight time skew for the setup condition:
Tsuskew  T flight DATA  T flight STB max
 Simplify the loop equation:
Tvb ,min  Tsu  Tsuskew  Tsumar
Signal Parameters & Timing Class 3
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Notes on the Setup Equation
 Tvb ,min  Tsu  Tsuskew  Tsumar
 You may see the timing equation
written in other forms.
 The way we defined Tvb makes it a
negative quantity. Others may define
it to be positive.
 We defined Tsuskew to be a positive
quantity.
Signal Parameters & Timing Class 3
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Hold Timing Diagram & Loop Analysis
TBCLK
BCLK
TBCLK/4
DCLK
Tco(STB)
Tco(DATA)
DRIVER STB/STB
Tflight(STB)
DRIVER
DATA
RECEIVER STB/STB
Tflight(DATA)
T
h
Thma
r
RECEIVER
TBCLK
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DATA
 Tco DATA  T flight DATA  Thmar  Thold  T flight STB   Tco STB   0
Signal Parameters & Timing Class 3
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Hold Analysis
TBCLK
4
 Tco DATA  T flight DATA  Thmar  Thold  T flight STB   Tco STB   0
 Just as for the setup case, we need to specify the
minimum phase relationship between data and
strobe: Tva ,min  Tco DATA  Tco STB   TBCLK
min
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 In addition, define the flight time skew for the
hold case:
Thskew  T flightDATA  T flightSTB min
 In addition, define the flight time skew for the
hold case: T
va , min  Thold  Thskew  Thmar
 Note that the Thskew is defined such that it is a
negative quantity, while Tva is defined to be
positive.
Signal Parameters & Timing Class 3
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Maximum Transfer Rate
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Tva,min
-Tvb,min
STB/STB
DATA
Tcycle,min
 The maximum transfer rate can be
determined using the definitions for Tva
and Tvb. T  4T  T DATA  T STB  
T
 4 T
 T DATA  T STB  
BCLK
BCLK

va , min
vb , min
co
co
co
min
co
max
We can calculate the limit of TBCLK (for a
double pumped bus) by adding the two
equations above.
TBCLK ,min  4 Tvb ,min  Tva ,min 
Signal Parameters & Timing Class 3
Higher Transfer Rates (e.g. “Quad Pumped”)
TBCLK
TBCLK
BCLK
BCLK
TBCLK/8
TBCLK/8
DCLK
DCLK
Tco(STB)
Tco(STB)
DRIVER STB/STB
Tco(DATA)
DRIVER
DRIVER STB/STB
Tflight(STB)
Tflight(STB)
DATA
DRIVER
Tflight(DATA)
DATA
DATA
RECEIVER STB/STB Tflight(DATA)
RECEIVER STB/STB
RECEIVER
Tco(DATA)
Tmargin
Tsetup
Thold
Tmargin
RECEIVER
DATA
 The setup and hold equations remain the same.
 What changes are the Tva and Tvb definitions:
Tvb  Tco DATA  Tco STB max 
TBCLK
Tva  Tco DATA  Tco STB min 
TBCLK
Signal Parameters & Timing Class 3
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Part C:
Edge Considerations and Real Specs
Signal Parameters & Timing Class 3
Review Edge Triggered Clocking
Data in
(d)
Data
out (Q)
D-Latch
clock
(clk)
Data in
(d)
Clock to out time or
data valid time
clock
(clk)
Hold
time
Data
out (Q)
Set up time
Signal Parameters & Timing Class 3
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Finer look at the latch
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Data in
 First stage is a
buffer
 Converts to internal
digital levels
 Its convenient to
think of buffer as
differential
Threshold
comparator
Data in
Signal Parameters & Timing Class 3
Internal output
Threshold
Buffer delay
time
Internal output
Switching Threshold
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 The transfer function of the Linear

input buffer is linear for
only for a very small region
on a input signals edge.
We want it to work in the
saturation region above and
below threshold.
Region
This is so the output is either is
high or low and converted to the
internal voltage representation of
high or low. I.e. binary
 The assumption is that the signal
edge is sufficiently fast enough to
guarantee predictable switching of
high to low and visa-versa.
Signal Parameters & Timing Class 3
Saturated
Region
SI engineers often
measure slew rate
as a reported
budget parameter
Vil and Vih
 Vil is the voltage

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Data in
required to switch the
output of the input
buffer to a low state.
Vih is the voltage
required to switch the
output of the input
buffer to a high state.
Signal Parameters & Timing Class 3
Vih
Vil
Relation to timing
 Transmitter output times are
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Transmitter out out into
reference load
measured at a threshold level.
This is how the Tco’s are
measured.
 Max and min values reported in
budgets are normally
Output Reference Threshold
The maximum of all the design
configuration and process
variations max values
The minimum of all the design
configurations and process
variations min values.
Min low going edge Flight time
Max high going edge Flight time
Input to Receiver
Vih
Min high going edge Flight time
Max low going edge Flight time
Signal Parameters & Timing Class 3
Vil
Assignment: Determine Tva and Tvb
 Give UI (unit interval =
10 ns)
Meaning 20ns period and
10ns bit time with
sufficiently fast rise
time
 The sources are 1 Volt




with source resistance
of 50 ohms
Data has 5pF tied to it
Strobe has 10p tied to
it.
The threshold voltage
VOL and VOH are 0.8 v
What are Tva and Tvb
Signal Parameters & Timing Class 3
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