Transcript Document

Introduction to
CMOS VLSI
Design
Circuit Characterization
and Performance
Estimation
Outline




Noise Margins
Transient Analysis
Delay Estimation
Logical Effort and Transistor Sizing
CMOS VLSI Design
Slide 2
Noise Margins
 How much noise can a gate input see before it does
not recognize the input?
Output Characteristics
Logical High
Output Range
VDD
Input Characteristics
NMH
VIH
VIL
NML
Logical Low
Output Range
Logical High
Input Range
VOH
VOL
Indeterminate
Region
Logical Low
Input Range
GND
CMOS VLSI Design
Slide 3
Logic Levels
 To maximize noise margins, select logic levels at
Vout
VDD
 p/ n > 1
Vin
Vout
Vin
0
VDD
CMOS VLSI Design
Slide 4
Logic Levels
 To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic
Vout
Unity Gain Points
Slope = -1
VDD
VOH
 p/ n > 1
Vin
VOL
Vin
0
Vtn
CMOS VLSI Design
Vout
VIL VIH VDD- VDD
|Vtp|
Slide 5
Transient Response
 DC analysis tells us Vout if Vin is constant
 Transient analysis tells us Vout(t) if Vin(t) changes
– Requires solving differential equations
 Input is usually considered to be a step or ramp
– From 0 to VDD or vice versa
CMOS VLSI Design
Slide 6
Inverter Step Response
 Ex: find step response of inverter driving load cap
Vin (t )  u (t  t0 )VDD
Vin(t)
Vout (t  t0 )  VDD
dVout (t )
I dsn (t )

dt
Cload

0


2

I dsn (t )  
V

V


DD
2

V (t )
  VDD  Vt  out 2
 
CMOS VLSI Design
Vout(t)
Cload
Idsn(t)
t  t0
Vout  VDD  Vt
 V (t ) V  V  V
 out
out
DD
t

Slide 7
Inverter Step Response
 Ex: find step response of inverter driving load cap
Vin (t )  u (t  t0 )VDD
Vin(t)
Vout (t  t0 )  VDD
Vout(t)
Cload
dVout (t )
I dsn (t )

dt
Cload

0


2

I dsn (t )  
V

V


DD
2

V (t )
  VDD  Vt  out 2
 
CMOS VLSI Design
Idsn(t)
Vin(t)
t  t0
Vout  VDD  Vt
 V (t ) V  V  V
 out
out
DD
t

Vout(t)
t0
t
Slide 8
Delay Definitions
 tpd: propagation delay time
– maximum time from input crossing 50% to output
crossing 50%
 tcd : contamination delay time
– minimum time from input crossing 50% to output
crossing 50%
 trf = (tr + tf )/2
 tr: rise time
– From output crossing 0.2 VDD to 0.8 VDD
 tf: fall time
– From output crossing 0.8 VDD to 0.2 VDD
CMOS VLSI Design
Slide 9
Delay Definitions
 tcdr: rising contamination delay
– From input crossing VDD/2 to rising output
crossing VDD/2
 tcdf: falling contamination delay
– From input crossing VDD/2 to falling output
crossing VDD/2
 tcd: average contamination delay
– tcd = (tcdr + tcdf)/2
CMOS VLSI Design
Slide 10
Simulated Inverter Delay
 Solving differential equations by hand is too hard
 SPICE simulator solves the equations numerically
– Uses more accurate I-V models too!
 But simulations take time to write
2.0
1.5
1.0
(V)
Vin
tpdf = 66ps
tpdr = 83ps
Vout
0.5
0.0
0.0
200p
400p
600p
800p
1n
t(s)
CMOS VLSI Design
Slide 11
Delay Estimation
 We would like to be able to easily estimate delay
– Not as accurate as simulation
– But easier to ask “What if?”
 The step response usually looks like a 1st order RC
response with a decaying exponential.
 Use RC delay models to estimate delay
– C = total capacitance on output node
– Use effective resistance R
– So that tpd = RC
 Characterize transistors by finding their effective R
– Depends on average current as gate switches
CMOS VLSI Design
Slide 12
RC Delay Models
 Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
 Capacitance proportional to width
 Resistance inversely proportional to width
d
g
d
k
s
kC
R/k
kC
2R/k
g
g
kC
kC
s
CMOS VLSI Design
s
d
k
s
kC
g
kC
d
Slide 13
Example: 3-input NAND
 Sketch a 3-input NAND with transistor widths
chosen to achieve effective rise and fall resistances
equal to a unit inverter (R).
CMOS VLSI Design
Slide 14
Example: 3-input NAND
 Sketch a 3-input NAND with transistor widths
chosen to achieve effective rise and fall resistances
equal to a unit inverter (R).
CMOS VLSI Design
Slide 15
Example: 3-input NAND
 Sketch a 3-input NAND with transistor widths
chosen to achieve effective rise and fall resistances
equal to a unit inverter (R).
2
2
2
3
3
3
CMOS VLSI Design
Slide 16
3-input NAND Caps
 Annotate the 3-input NAND gate with gate and
diffusion capacitance.
2
2
2
3
3
3
CMOS VLSI Design
Slide 17
3-input NAND Caps
 Annotate the 3-input NAND gate with gate and
diffusion capacitance. Cg is approximately equal to
Cdiff in many processes.
2C
2
2C
2C
2C
2
2C
2
2C
3C
3C
3C
CMOS VLSI Design
2C
2C
2C
3
3
3
3C
3C
3C
3C
Slide 18
In a good layout, diffusion nodes are shared wherever
possible to reduce the diffusion capacitance
The uncontacted diffusion nodes between series
transistors are smaller than the contacted diffusion
nodes.
CMOS VLSI Design
Slide 19
3-input NAND Caps
 Annotate the 3-input NAND gate with gate and
diffusion capacitance.
2
2
3
5C
5C
5C
CMOS VLSI Design
2
3
3
9C
3C
3C
Slide 20
Elmore Delay
 ON transistors look like resistors
 Pullup or pulldown network modeled as RC ladder
 Elmore delay of RC ladder
t pd 

Ri to  sourceCi
nodes i
 R1C1   R1  R2  C2  ...   R1  R2  ...  RN  C N
R1
CMOS VLSI Design
R2
R3
C1
C2
RN
C3
CN
Slide 21
Example: 2-input NAND
 Estimate worst-case rising and falling delay of 2input NAND driving h identical gates.
2
2
A
2
B
2x
CMOS VLSI Design
Y
h copies
Slide 22
Example: 2-input NAND
 Estimate rising and falling propagation delays of a 2input NAND driving h identical gates.
2
2
A
2
B
2x
CMOS VLSI Design
6C
Y
4hC
h copies
2C
Slide 23
Example: 2-input NAND
 Estimate rising and falling propagation delays of a 2input NAND driving h identical gates.
2
2
A
2
B
2x
R
Y
(6+4h)C
CMOS VLSI Design
6C
Y
4hC
h copies
2C
t pdr 
Slide 24
Example: 2-input NAND
 Estimate rising and falling propagation delays of a 2input NAND driving h identical gates.
2
2
A
2
B
2x
R
Y
(6+4h)C
CMOS VLSI Design
6C
Y
4hC
h copies
2C
t pdr   6  4h  RC
Slide 25
Example: 2-input NAND
 Estimate rising and falling propagation delays of a 2input NAND driving h identical gates.
2
2
A
2
B
2x
CMOS VLSI Design
6C
Y
4hC
h copies
2C
Slide 26
Estimate the worst case falling propagation delays
of a 2-input NAND driving h identical gates
The worst case occurs when the node x is already
charged up to nearly Vdd through the top nMOS
2
2
A
2
B
2x
6C
2C
Y
4hC
Suppose A = 1, B = 0, then
Y = 1, node X is nearly VDD
Now change inputs to A=B=1
both node Y and node X need
to discharge
CMOS VLSI Design
Slide 27
Example: 2-input NAND
 Estimate rising and falling propagation delays of a 2input NAND driving h identical gates.
2
2
A
2
B
2x
x
R/2
R/2
2C
CMOS VLSI Design
Y
(6+4h)C
Y
4hC
6C
h copies
2C
t pdf 
Slide 28
Example: 2-input NAND
 Estimate rising and falling propagation delays of a 2input NAND driving h identical gates.
2
2
A
2
B
2x
x
R/2
R/2
2C
CMOS VLSI Design
Y
(6+4h)C
6C
Y
4hC
h copies
2C
t pdf   2C   R2    6  4h  C   R2  R2 
  7  4h  RC
Slide 29
Delay Components
 Delay has two parts
– Parasitic delay, gate driving its own internal
diffusion capacitance
• 6 or 7 RC
• Independent of load
– Effort delay, depends on the ration of external
load capacitance to input capacitance,
– Effort delay changes with transistor width
• Proportional to load capacitance
• Logical effort and Electrical effort
CMOS VLSI Design
Slide 30
Contamination Delay
 Best-case (contamination) delay can be substantially
less than propagation delay.
 Ex: If both inputs fall simultaneously, the output
should be pulled up in half the time
2
2
A
2
B
2x
R R
Y
(6+4h)C
CMOS VLSI Design
6C
Y
4hC
2C
tcdr = (R/2)(6+4h)C
tcdr   3  2h  RC
Slide 31
Diffusion Capacitance
 we assumed contacted diffusion on every s / d.
 Good layout minimizes diffusion area
 Ex: NAND3 layout shares one diffusion contact
– Reduces output capacitance by 2C
– Merged uncontacted diffusion might help too
2C
Shared
Contacted
Diffusion
Isolated
Contacted
Diffusion
Merged
Uncontacted
Diffusion
2
2
2
3
3
3C 3C 3C
CMOS VLSI Design
2C
3
7C
3C
3C
Slide 32
Layout Comparison
 Which layout is better?
VDD
A
VDD
B
Y
GND
CMOS VLSI Design
A
B
Y
GND
Slide 33