Transcript 슬라이드 1

Thin Film Encapsulation of Acceleration Sensors
Using PolySilicon Sacrificial Layers
H,Stahl1, A.Hoechst1, F.Fischer1, L.Metzger1, R.Reichenbach1,F.Laermer1,
S.Kronmueller1, K.Breitschwerdt1,
R.Gunn2, S.Watcham2, C.Rusu3, and A.Witvrouw3
1Robert
Bosch GmbH, Reutlingen and Stuttgart, Germany,
2Surface Technology Systems plc, Newport, United Kingdom,
3IMEC, Leuven, Belgium
04.11.26
이종규
Abstract
» This work presents a novel wafer encapsulation technique for MEMS devices.
» Advantages
- low area consumption
- reduced thickness of the sealed device
- CMOS compatible process flow for a MEMS 1st CMOS intergrated sensor
» Main features
- use of a 2nd sacrificial layer on top of the device made from Si
- a thick cap layer also made from Si and use the gas ClF3 for the etching of
the sacrificial Si layer)
» Mechanical stability
- the mechanical stability of the cap layer during handling of plastic mold
packaging is ensured by a barrel vault design of the MEMS cavity
Introduction
» Unlike CMOS chips, MEMS devices packaged directly in their special housing
» Protect fragile MEMS structures
- Why? : MEMS devices often need special working conditions such as a
vacuum enclosure, thermal contact to the outside world.
- How? : packaging of the devices while they are still on wafer level.
attaching a second wafer as a cap to the wafer
» Another approach for the encapsulation
- make use of a cap layer deposited directly on the device wafer.
- the movable part of the device needs two sac. layers,
one below the functional layer and one on top it
- Problem : etch rate, stiction, stress in thick layers, etc.
- Alternative : use of Si sac. layer with a new sacrificial etching technique
featuring ClF3 or XeF2
Experimental Procedure 1
» Process sequence of sensor of this kind
- sequential deposition
- patterning of the buried interconnect layer, the bottom sac. layer,
the functional MEMS layer, the top sac. layer, and the cap layer.
» Main issue
- protection of the functional & cap layers (made from Si)
- achieved by passivating all Si structures not to be etched
with a thin oxide layer (≈100 nm)
- the sac. layer needs to be separated from the functional & cap layers
- Different oxides have been characterized regarding their passivation
properties against ClF3
- The encapsulation process uses thermal oxides for extremely thin
passivation(100 nm) and TEOS oxides for thicker passivation or
for confromal deposition on high aspect ratio structures.
* TEOS(Tetra-ethyl-ortho-silicate)
Experimental Procedure 2
sealing frame ; support for cap
barrel vault
movable electrode
cross section
for next fig2(a-d)
fixed electrodes
< Figure 1 >
» Supporting the cap layer by introducing barrel vaults in the sensor core
Si functional layer
SiO2 bottom sac. layer
Substrate
< Figure 2a >
» Before depositing Top sac. Si layer, the sensor has to be protected against
the future sac. etching process by depositing a 200 nm thick TEOS oxide
Experimental Procedure 3
Si top sacrificial layer
< Figure 2b >
» Si top sac. layer deposited, patterned and passivated, yielding a precisely
confined volume for sac. etching.
» Si top sac. layer consists of a thin poly-Si seed layer and an approximately
8 mm thick Si layer grown in an epitaxy reactor
Experimental Procedure 4
etch
access
holes
Si cap layer
< Figure 2c >
» Si cap layer deposited by epitaxial growth on a poly-Si seed layer
and is planarized by CMP to enable further lithography steps.
» Etch access holes patterned via DRIE using a thick SiO2 hard mask
oxide passivation at bottom of access holes opened for sac. etching.
» The cap layer has s final thickness of 20 mm. –【Fig4】
Experimental Procedure 5
sealing oxide
top layer
bottom layer
< Figure 2d >
» Completed MEMS sensor after sac. etching with ClF3( top layer ) and
HF( bottom layer & passivation oxides ) and sealed by non-conformal
deposition of a PECVD oxide layer.
sealing oxide
Si cap layer
Si top sac. layer
Si functional layer
SiO2 bottom sac. layer
Substrate
sealing oxide
Si cap layer
Si top sac. layer
Si functional layer
SiO2 bottom sac. layer
Substrate
Substrate
Deposition of Si cap layer
SiO2 bottom sac. layer
Etch access holes patterned
Si functional sac. layer
HF etching ( bottom sac. layer
passivation oxides )
Deposition of 200 nm TEOS oxide
ClF3 etching ( top sac. layer )
Deposition of Si top sac. layer
Vent hole are sealed by PECVD
Experimental Results 1
< Figure 3>
< Figure 4 >
» SEM of a sensor structure covered with a thin TEOS oxide(200 nm) and
silicon top sac. layer deposited and planarized –【Fig 3】
» Voids in the gaps of the sensor structure will disappear during sac. etching.
–【Fig 3】
» The sac. layer is thinner than the functional layer, so the cap & substrate
can work as overtravel stops in z-direction. –【Fig 4】
Experimental Results 2
< Figure 5>
< Figure 6 >
» SEM of a device with the etch access holes etched into the cap layer.
The side walls are passivated by a thin thermal oxide.–【Fig 5】
» The top sac. etching –【Fig 6】
- etch rate : 4 mm/min
- Selectivity(silicon to therma oxide) → 1000:1
Experimental Results 3
< Figure 7 >
» After sac. etching, the vent holes are sealed by depositing a non-conformal
PECVD oxide on the wafer
» During this step, the ambient conditions of the devices are set by enclosing
either a vacuum or a certain atmosphere determined by the sealing process.
Conclusion
» A new WLP technique for MEMS devices was demonstrated
» The sac. etching was done by gaseous etching of the Si sacrificial
layer with ClF3.
» Cap and functional layer were protected by thin oxide layers
during etch.
» The main advantages
- a reduced area consumption
- fast & easy sacrificial etching
- a completely CMOS compatible process flow