Transcript Slide 1

EL402 VLSI System Design II
Spring 2009
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Instructor: Ilker Hamzaoglu
[email protected]
MDBF 1037
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Teaching Assistant: Onur Can Ulusel
[email protected]
MDBF 1042
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Web Site: http://people.sabanciuniv.edu/~hamzaoglu/el402/el402.htm
EL 402
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Course Structure
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EL 402 3.00 VLSI Systems Design II
M 11:40 am - 12:30 pm FENS L058
R 11:40 am - 1:30 pm FENS L058
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EL 402R 0.00 VLSI Systems Design II Rec.
M 12:40 pm - 1:30 pm FENS L058
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Course Description
• This course introduces System-on-a-chip (SoC) ASICs and it
describes various embedded cores used in SoC ASICs. It then
discusses the design and verification of SoC ASICs. In this
course, students will also gain practical design experience by
using Arm7 simulation model, Modelsim (Mentor Graphics) and
Design Compiler (Synopsys) CAD tools to implement and verify
a prototype SoC ASIC. The SoC ASIC will be implemented
using Verilog HDL and standard cell based design methodology.
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References
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Lecture Slides
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Arm Inc. (http://www.arm.com) Technical Documents (Technical
Specifications, Technical Reference Manuals, White Papers, and
Company Presentations)
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Textbooks:
– ARM System-on-chip Architecture, Steve Furber, Addison Wesley,
2nd Edition, 2000
– Computers as Components: Principles of Embedded Computing
System Design, Wayne Wolf, Morgan Kaufmann, 2nd Edition, 2005
– Reuse Methodology Manual for System-on-a-Chip Designs,
Michael Keating, Pierre Bricaud, Russell John Rickford, Kluwer
Academic Publishers, 3rd Edition, July 2002
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Tentative Schedule
• Introduction
– System-on-a-chip (SoC) ASICs
– Core-based and Platform-based Design
• SoC Embedded Cores
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Embedded Microprocessors, Arm Cores
Hardware Accelerators
On-chip Interconnects, Arm AMBA
Memory Controllers, DMA, Interrupt Controller
Device Interfaces, Image Sensor Interface
• SoC ASIC Design
– System Level (Architecture) Design
– Behavioral (Architectural) Modeling, SystemC
– Behavioral (Architectural) Synthesis
• SoC ASIC Verification
• SoC ASIC Debugging
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SoC ASIC Design Project
TestBench
Arm7TDMI
(Model)
Clock
Dividers
PLL
(Model)
Crystal
Oscillator
(Model)
Arm7
Cache
Image
Processing
Accelerator
Register
Files
Image
Sensor
Interface
Image Sensor
(Model)
AHB Bus
AHB Bus
Decoder
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AHB Bus
Mux
SRAM
Controller
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SRAM
(Model)
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Grading
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Attendance
SoC ASIC Design Project
Paper Presentation
Final Exam
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Students will work in groups of two for the project. The project will be
done using the Sun Workstations in the VLSI Design Lab which is
located in MDBF 1062.
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Cheating in the project and the exam is not allowed. It will be strongly
penalized.
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40%
10%
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