Transcript Slide 1
Studies on Single DC link Fed Multilevel Inverter Topologies Using Flying Capacitor And Floating Capacitor Fed H-Bridges
P. Roshan Kumar Research Supervisor: Prof. K. Gopakumar DESE, IISc, Bangalore DESE, Indian Institute of Science Bangalore
Overview of Presentation Overview of multilevel inverters Five level inverter topology Common mode voltage eliminated three level inverter Seventeen-level inverter topology Back to back connected multilevel inverter DESE, Indian Institute of Science Bangalore
Multilevel inverters Applications in medium and high voltage drives above 1kV Reliable operation of devices beyond 1200V are not practical with two level inverters Voltage balancing of devices in a series connection is very difficult Need transformers to generate higher voltages from a low voltage inverter hence extra cost DESE, Indian Institute of Science Bangalore
Advantages of Multilevel inverters The voltage waveforms are close to sinusoid Reduced harmonics distortion Reduced filtering requirements Reduced current ripple Reduced heating of magnetics and capacitors Lower switching frequencies of devices Reduced switching losses (Distributed losses) Reduced EMI DESE, Indian Institute of Science Bangalore
Fields of Research in Multilevel inverters Reliable topologies Ease of control and reduced complexity Stability of the output voltage level Optimized number of active and passive devices Modularity of the systems DESE, Indian Institute of Science Bangalore
Part I
A Five Level Inverter Topology With Single DC-Supply By Cascading Flying Capacitor Inverter and H-Bridge
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Proposed Five-level Inverter One phase Schematic Possible voltage levels.
0 Vdc/4 Vdc/2 3Vdc/4 Vdc O DESE, Indian Institute of Science Bangalore
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O State for Voltage level 0 I State ( 0, 0, 0, 0 ) C1 : No effect C2 : No effect DESE, Indian Institute of Science Bangalore
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O Redundant States for pole voltage of V DC /4 I State ( 0, 0, 0, 1 ) C1 : No effect C2 : Discharge I State ( 0, 1, 1, 0 ) C1 : Discharge C2 : Charge O I State ( 1, 0, 1, 0 ) C1 : Charge C2 : Charge O DESE, Indian Institute of Science Bangalore
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Redundant States for pole voltage of V DC /4 DESE, Indian Institute of Science Bangalore
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Redundant States for pole voltage of V DC /2 I State ( 1, 0, 0, 0 ) C1 : Charge C2 : No effect O O I State ( 0, 1, 0, 0 ) C1 : Discharge C2 : No effect DESE, Indian Institute of Science Bangalore
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O Redundant States for pole voltage of 3V DC /4 I State ( 0, 1, 0, 1 ) C1 : Discharge C2 : Discharge I State ( 1, 0, 0, 1 ) C1 : Charge C2 : Discharge O I State ( 1, 1, 1, 0 ) C1 : No Effect C2 : Charge O DESE, Indian Institute of Science Bangalore
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O Redundant States for pole voltage of V DC I State ( 1, 1, 1, 1 ) C1 : No effect C2 : No effect DESE, Indian Institute of Science Bangalore
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Three phase Circuit Diagram DESE, Indian Institute of Science Bangalore
Possible Space Vector voltage states Voltage levels in A phase 0 Vdc/4 Vdc/2 3Vdc/4 Vdc DESE, Indian Institute of Science Bangalore
Possible Space Vector voltage states Voltage levels in A and B Phases DESE, Indian Institute of Science Bangalore
Possible Space Vector voltage states Voltage levels in A, B and C Phases DESE, Indian Institute of Science Bangalore
Five Level Three Phase Space Vector Polygon
Sector-I
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Sector-I (60 degree) Voltage States and Redundancies
Voltage Ref
0: 0 1: Vdc/4 2: Vdc/2 3: 3Vdc/4 4: Vdc
State
0 1 2 7 8 9 19 20 21 22 37 38 39 40 41
Voltage combinations of three phases
(0,0,0) (1,1,1) (2,2,2,) (3,3,3) (4,4,4) (1,0,0) (2,1,1) (3,2,2) (4,3,3) (1,1,0) (2,2,1) (3,3,2) (4,4,3) (2,0,0) (3,1,1) (4,2,2) (2,1,0) (3,2,1) (4,3,2) (2,2,0) (3,3,1) (4,4,2) (3,0,0) (4,1,1) (3,1,0) (4,2,1) (3,2,0) (4,3,1) (3,3,0) (4,4,1) (4,0,0) (4,1,0) (4,2,0) (4,3,0) (4,4,0) DESE, Indian Institute of Science Bangalore
Redundancies
5 4 4 3 3 3 2 2 2 2 1 1 1 1 1
Controller block diagram Level shifted carrier based PWM is used to generate the three phase voltage.
Controller was realized using TMS320F2812 DSP along with SPARTAN-3 XC3S200 FPGA to generate all the 48 PWM signals. All the capacitor voltage levels are sensed and compared with reference values using hysteresis comparator 3-Phase Y-connected 400V, 50Hz, SCIM is run in open loop V/f algorithm.
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PWM generation for multilevel inverters (a) the reference wave before and after the addition of the common-mode voltage and the four level shifted carriers (b) the reference waveform after translating into the innermost carrier region.
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Level shifted carrier based PWM V DC 3V DC /4 V DC /2 V DC /4 0 V DC /4 0 (a) the reference wave before and after the addition of the common-mode voltage and the four level shifted carriers (b) the reference waveform after translating into the innermost carrier region.
DESE, Indian Institute of Science Bangalore
Experimental Setup and Results A 3KW,400V 50Hz, Induction machine is run in V/f Mode Level- shifted carrier based SV-PWM algorithm is implemented on TMS320F2812 DSP and Xilinx SPARTAN-3 XC3S200 FPGA Dead time of 3 µS Motor is run at various modulation indices MI = 0.2 at 10Hz MI = 0.4 at 20Hz MI = 0.6 at 30Hz MI = 0.8 at 40Hz Sudden acceleration to test the capacitor balancing algorithm Capacitor balancing algorithm is disabled and re enabled to see the response of the controller DESE, Indian Institute of Science Bangalore
Phase and Pole Voltage for 10 Hz V AN: Phase Voltage (50V/div) IA : Phase Current (2A/div) VC1: Cap1 Voltage Ripple (5V/div) VC2: Cap2 Voltage Ripple (10V/div) Time scale: 20mS/div V A0: Pole Voltage (50V/div) IA : Phase Current (2A/div) VC1: Cap1 Voltage Ripple (5V/div) VC2: Cap2 Voltage Ripple (10V/div) Time scale: 20mS/div DESE, Indian Institute of Science Bangalore
Phase and Pole Voltage for 20 Hz V AN: Phase Voltage (100V/div) IA : Phase Current (2A/div) VC1: Cap1 Voltage Ripple (5V/div) VC2: Cap2 Voltage Ripple (10V/div) Time scale: 10mS/div V A0: Pole Voltage (100V/div) IA : Phase Current (2A/div) VC1: Cap1 Voltage Ripple (5V/div) VC2: Cap2 Voltage Ripple (10V/div) Time scale: 10mS/div DESE, Indian Institute of Science Bangalore
Phase and Pole Voltage for 30 Hz V AN: Phase Voltage (100V/div) IA : Phase Current (2A/div) VC1: Cap1 Voltage Ripple (5V/div) VC2: Cap2 Voltage Ripple (10V/div) Time scale: 10mS/div V A0: Pole Voltage (100V/div) IA : Phase Current (2A/div) VC1: Cap1 Voltage Ripple (5V/div) VC2: Cap2 Voltage Ripple (10V/div) Time scale: 10mS/div DESE, Indian Institute of Science Bangalore
Phase and Pole Voltage for 40 Hz V AN: Phase Voltage (100V/div) IA : Phase Current (2A/div) VC1: Cap1 Voltage Ripple (5V/div) VC2: Cap2 Voltage Ripple (10V/div) Time scale: 5mS/div V A0: Pole Voltage (100V/div) IA : Phase Current (2A/div) VC1: Cap1 Voltage Ripple (5V/div) VC2: Cap2 Voltage Ripple (10V/div) Time scale: 5mS/div DESE, Indian Institute of Science Bangalore
Capacitor Voltage under sudden acceleration The motor is accelerated from 10Hz to 40Hz at no load and the capacitor voltages are almost constant in this duration V AN: Phase Voltage (200V/div) IA : Phase Current (2A/div) VC1: Cap1 DC Voltage (200V/div) VC2: Cap2 DC Voltage (50V/div) Time scale: 1S/div DESE, Indian Institute of Science Bangalore
Capacitor Balancing Algorithm Test The Capacitor balancing algorithm has been disabled for C1 and C2 at T1, enabled for C1 at T2 and C2 at T3.
V AN: Phase Voltage (200V/div) IA : Phase Current (2A/div) VC1: Cap1 DC Voltage (200V/div) VC2: Cap2 DC Voltage (50V/div) Time scale: 2S/div DESE, Indian Institute of Science Bangalore
Component Comparison With Standard Inverters
Component
Capacitor (Vdc/4) Switches (Vdc/4) Switches (Vdc/2) Clamping Diodes (Vdc/2) Power Supplies (Vdc/4) Power Supplies (Vdc)
NPC
4 24 0 36 0 1
FC
18 24 0 0 0 1 NPC : Neutral Point Clamped Inverter FC : Flying Capacitor Inverter CHB : Cascaded H-Bridge Inverter PI : Proposed Inverter Configuration
CHB
6 24 0 0 6 0
PI
6 12 12 0 0 1 DESE, Indian Institute of Science Bangalore
Reliable Operation In case of device failures in H-Bridge, the configuration can work as 3 level inverter at full power rating at all modulation indices there by improving the fault operability of the configuration S3 or S4 open fault S3`or S4` short fault S3 or S4 short fault S3`or S4` open fault DESE, Indian Institute of Science Bangalore
Conclusion A novel five-level inverter with single DC link has been proposed, analyzed and implemented in hardware.
The performance of the inverter is tested by running a three phase induction motor at no load and the voltages and currents are analyzed both during steady state and during transients at various modulation indices and frequencies.
Use if single DC supply enables back to back connection where multiple sources and loads can interact over single DC link.
Important feature is fault tolerant reliable operation at full load. If one of H Bridges fail, the inverter can still be operated at full load by bypassing the faulty h bridge and operating the inverter as a three-level inverter.
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Part II
Common-Mode Voltage Eliminated Three-Level Inverter using a Three-Level Flying Capacitor Inverter and Cascaded H-Bridge
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Three Level Inverter with Zero Common Mode Voltage The common mode voltage of the induction motor connected in single ended configuration is given by V CM = (V A + V B + V C )/3 DESE, Indian Institute of Science Bangalore
Five Level Three Phase Space Vector Polygon
Sector-I
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Sector-I (60 degree) Voltage States and Redundancies
Voltage Ref
-2 : -Vdc/2 -1 : -Vdc/4 0 : 0 1: Vdc/4 2: Vdc/2
State
0 1 2 7 8 9 19 20 21 22 37 38 39 40 41
Voltage combinations of three phases
(-2,-2,-2) (-1,-1,-1) (0,0,0,) (1,1,1) (2,2,2) (-1,-2,-2) (0,-1,-1) (1,0,0) (2,1,1) (-1,-1,-2) (0,0,-1) (1,1,0) (2,2,1) (0,-2, -2) (1,-1,-1) (2,0,0) (0,-1,-2) (1,0,-1) (2,1,0) (0,0,-2) (1,1,-1) (2,2,0) (1,-2,-2) (2,-1,-1) (1,-1,-2) (2,0,-1) (1,0,-2) (2,1,-1) (1,1,-2) (2,2,-1) (2,-2,-2) (2,-1,-2) (2,0,-2) (2,1,-2) (2,2,-2) DESE, Indian Institute of Science Bangalore
Redundancies
5 4 4 3 3 3 2 2 2 2 1 1 1 1 1
5-Level States with zero common mode voltage Values of (a, b, c) -2 = -Vdc/2 -1 = -Vdc/4 0 = 0 1 = Vdc/4 2 = Vdc/2
S. No
14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13
SV location (5-Level Polygon)
39 43 47 51 55 59 0 8 10 12 14 16 18 19 22 25 28 31 34
Combination (a, b, c)
(0,0,0) (1,0,-1) (0,1,-1) (-1,1,0) (-1,0,1) (0,-1,1) (1,-1,0) (2,-1,-1) (1,1,-2) (-1,2,-1) (-2,1,1) (-1,-1,-2) (1,-2,1) (2,0,-2) (0,2,-2) (-2,2,0) (-2,0,2) (0,-2,2) (2,-2,0) DESE, Indian Institute of Science Bangalore
Location of States with Zero Common mode Voltage DESE, Indian Institute of Science Bangalore
Location of States with Zero Common mode Voltage DESE, Indian Institute of Science Bangalore
Location of States with Zero Common mode Voltage DESE, Indian Institute of Science Bangalore
Experimental Setup and Results A 3KW,400V 50Hz, Induction machine is run in V/f Mode Level- shifted carrier based SV-PWM algorithm is implemented on TMS320F2812 DSP and Xilinx SPARTAN-3 XC3S200 FPGA Dead time of 3 µS Motor is run at various modulation indices MI = 0.2 at 10Hz MI = 0.4 at 20Hz MI = 0.6 at 30Hz MI = 0.8 at 40Hz Sudden acceleration to test the capacitor balancing algorithm Capacitor balancing algorithm is disabled and re enabled to see the response of the controller DESE, Indian Institute of Science Bangalore
Controller block Diagram DESE, Indian Institute of Science Bangalore
Phase and Pole Voltage for 10 Hz V AO: Pole Voltage (100V/div) V AN : Phase Voltage (100V/div) VNO: Common-mode Voltage (20V/div) IA: Phase Current (2A/div)Cap2 Time scale: 20mS/div V AO: Pole Voltage (100V/div) VC1: Cap1(Vdc/2) Voltage (50V/div) VC2: Cap2(Vdc/4) Voltage (50V/div) IA : Phase Current (2A/div) Time scale: 20mS/div DESE, Indian Institute of Science Bangalore
Phase and Pole Voltage for 20 Hz V AO: Pole Voltage (100V/div) V AN : Phase Voltage (100V/div) VNO: Common-mode Voltage (20V/div) IA: Phase Current (2A/div)Cap2 Time scale: 10mS/div V AO: Pole Voltage (50V/div) VC1: Cap1(Vdc/2) Voltage (50V/div) VC2: Cap2(Vdc/4) Voltage (50V/div) IA : Phase Current (2A/div) Time scale: 10mS/div DESE, Indian Institute of Science Bangalore
Phase and Pole Voltage for 30 Hz V AO: Pole Voltage (100V/div) V AN : Phase Voltage (100V/div) VNO: Common-mode Voltage (20V/div) IA: Phase Current (2A/div)Cap2 Time scale: 10mS/div V AO: Pole Voltage (100V/div) VC1: Cap1(Vdc/2) Voltage (50V/div) VC2: Cap2(Vdc/4) Voltage (50V/div) IA : Phase Current (2A/div) Time scale: 10mS/div DESE, Indian Institute of Science Bangalore
Phase and Pole Voltage for 40 Hz V AO: Pole Voltage (100V/div) V AN : Phase Voltage (100V/div) VNO: Common-mode Voltage (20V/div) IA: Phase Current (2A/div)Cap2 Time scale: 5mS/div V AO: Pole Voltage (100V/div) VC1: Cap1(Vdc/2) Voltage (10V/div) VC2: Cap2(Vdc/4) Voltage (50V/div) IA : Phase Current (2A/div) Time scale: 5mS/div DESE, Indian Institute of Science Bangalore
Phase and Pole Voltage for 50 Hz V AO: Pole Voltage (100V/div) V AN : Phase Voltage (100V/div) VNO: Common-mode Voltage (20V/div) IA: Phase Current (2A/div)Cap2 Time scale: 5mS/div V AO: Pole Voltage (100V/div) VC1: Cap1(Vdc/2) Voltage (50V/div) VC2: Cap2(Vdc/4) Voltage (50V/div) IA : Phase Current (2A/div) Time scale: 5mS/div DESE, Indian Institute of Science Bangalore
Capacitor Voltage Under Sudden Acceleration The motor is accelerated from 10Hz to 40Hz at no load and the capacitor voltages are almost constant in this duration V AN: Phase Voltage (100V/div) VC2: Cap2(Vdc/4) Voltage ripple (2V/div) VCM: Common mode Voltage (10V/div) IA : Phase Current (2A/div) Time scale: 500mS/div DESE, Indian Institute of Science Bangalore
Capacitor Balancing Algorithm Test The Capacitor balancing algorithm has been disabled for C1 and C2 at T1, enabled for C1 at T2 and C2 at T3.
VC1: Cap1(Vdc/2) Voltage (50V/div) VC2: Cap2(Vdc/4) Voltage (50V/div) VCM: Common-mode Voltage (10V/div) IA : Phase Current (10A/div) Time scale: 500mS/div DESE, Indian Institute of Science Bangalore
Reliable Operation In case of device failures in H-Bridge, the configuration can work as a normal 3 level inverter at full power rating at all modulation indices there by improving the fault operability of the configuration S3 or S4 open S3’or S4’ short S3 or S4 short S3’or S4’ open DESE, Indian Institute of Science Bangalore
Part III
A Seventeen-level Inverter With a Single DC-link For Motor Drives
DESE, Indian Institute of Science Bangalore
Overview Introduction 17 level inverter Power Circuit Capacitor balancing SV- Polygon and discussion Experimental results Salient Features DESE, Indian Institute of Science Bangalore
Possible voltage levels with the proposed configuration Each level of cascading can generate 3 individual voltage levels.
The total number of voltage levels are arithmetic combinations of the voltages from 3 states.
Total of 31 possible pole voltage levels Each cascaded H-bridge has a floating capacitor with capacitor voltage balanced at prescribed value.
Can generate 17 pole voltage levels where all capacitor voltages can be balanced( 0, Vdc/16, Vdc/8, 3Vdc/16, Vdc/4, 5Vdc/16, 3Vdc/8, 7Vdc/16, Vdc/2, 9Vdc/16, 5Vdc/8, 11Vdc/16, 3Vdc/4, 13Vdc/16, 7Vdc/8, 15Vdc/16 and Vdc) DESE, Indian Institute of Science Bangalore
3-Phase 17-level Power Circuit With Single DC link DESE, Indian Institute of Science Bangalore
A Phase17-level Power Circuit With Single DC link Single DC link Power Supply.
Can generate 17 pole voltage levels.
Total of 16 devices per phase Total of 4 Capacitors per phase All capacitors can be balanced at all 17 pole voltage levels Faithful reproduction of commanded voltage at all load power factors and currents DESE, Indian Institute of Science Bangalore
Voltage states and effect on Capacitors for positive direction of current
S.No
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pole Voltage
0 Vdc/16 Vdc/8 3Vdc/16 Vdc/4
Switch State
(0,0,0,0,0,0,0,0) (0,0,0,0,0,0,0,1) (0,0,0,0,0,1,1,0) (0,0,0,1,1,0,1,0) (0,1,1,0,1,0,1,0) (1,0,1,0,1,0,1,0) (0,0,0,0,0,1,0,0) (0,0,0,1,1,0,0,0) (0,1,1,0,1,0,0,0) (1,0,1,0,1,0,0,0) (0,0,0,0,0,1,0,1) (0,0,0,1,0,0,1,0) (0,0,0,1,1,0,0,1) (0,1,1,0,0,0,1,0) (0,1,1,0,1,0,0,1) (1,0,1,0,0,0,1,0) (1,0,1,0,1,0,0,1) (0,0,0,1,0,0,0,0) (0,1,1,0,0,0,0,0) (1,0,1,0,0,0,0,0)
C1 a
0 0 0 0 + 0 0 + 0 + + 0 0 0 +
C2 a
0 0 0 + + 0 + + + + + 0 + + +
C3 a
0 0 + + + + + 0 0 0 + + 0 + 0 + 0
C4 a
0 + + + + 0 0 0 0 0 0 0 + + +
S.No
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Pole Voltage
5Vdc/16 3 Vdc/8 7 Vdc/16 Vdc/2
Switch State
(0,0,0,1,0,0,0,1) (0,0,0,1,0,1,1,0) (0,1,0,0,1,0,1,0) (0,1,1,0,0,0,0,1) (0,1,1,0,0,1,1,0) (1,0,0,0,1,0,1,0) (1,0,1,0,0,0,0,1) (1,0,1,0,0,1,1,0) (0,0,0,1,0,1,0,0) (0,1,0,0,1,0,0,0) (0,1,1,0,0,1,0,0) (1,0,0,0,1,0,0,0) (1,0,1,0,0,1,0,0) (0,0,0,1,0,1,0,1) (0,1,0,0,0,0,1,0) (0,1,0,0,1,0,0,1) (0,1,1,0,0,1,0,1) (1,0,0,0,0,0,1,0) (1,0,0,0,1,0,0,1) (1,0,1,0,0,1,0,1) (0,1,0,0,0,0,0,0)
C1 a
0 0 + + + + + + 0 + + 0 -
C2 a
0 + + 0 + + + 0 0 + 0 0 + 0 + 0 0
C4 a
+ + + + + + 0 0 0 0 0 0 + -
C3 a
0 + 0 + 0 0 + 0 + + 0 + +,-,0 indicates charging, discharging and no effect of capacitor for postive direction of current.
C1 = Vdc/2 Capacitor, C2 = Vdc/4 Capacitor, C3 = Vdc/8 Capacitor, C1 = Vdc/16 Capacitor DESE, Indian Institute of Science Bangalore
Voltage states and effect on Capacitors for positive direction of current
S.No
42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Pole Voltage
Vdc/2 9 Vdc/16 5 Vdc/8 11 Vdc/16
Switch State
(1,0,0,0,0,0,0,0) (0,1,0,0,0,0,0,1) (0,1,0,0,0,1,1,0) (0,1,0,1,1,0,1,0) (1,0,0,0,0,0,0,1) (1,0,0,0,0,1,1,0) (1,0,0,1,1,0,1,0) (1,1,1,0,1,0,1,0) (0,1,0,0,0,1,0,0) (0,1,0,1,1,0,0,0) (1,0,0,0,0,1,0,0) (1,0,0,1,1,0,0,0) (1,1,1,0,1,0,0,0) (0,1,0,0,0,1,0,1) (0,1,0,1,0,0,1,0) (0,1,0,1,1,0,0,1) (1,0,0,0,0,1,0,1) (1,0,0,1,0,0,1,0) (1,0,0,1,1,0,0,1) (1,1,1,0,0,0,1,0) (1,1,1,0,1,0,0,1)
C1 a
+ + + + 0 + + + 0 0 + + 0 -
C2 a
0 0 0 0 0 + 0 + + 0 0 + 0 -
C3 a
0 0 + 0 + + 0 + 0 + + + + 0 +
C4 a
0 + + + + + + + 0 0 0 0 0 + -
S.No
63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 Pole Voltage
3 Vdc/4 13 Vdc/16 7 Vdc/8 15 Vdc/16 Vdc
Switch State
(0,1,0,1,0,0,0,0) (1,0,0,1,0,0,0,0) (1,1,1,0,0,0,0,0) (0,1,0,1,0,0,0,1) (0,1,0,1,0,1,1,0) (1,0,0,1,0,0,0,1) (1,0,0,1,0,1,1,0) (1,1,0,0,1,0,1,0) (1,1,1,0,0,0,0,1) (1,1,1,0,0,1,1,0) (0,1,0,1,0,1,0,0) (1,0,0,1,0,1,0,0) (1,1,0,0,1,0,0,0) (1,1,1,0,0,1,0,0) (0,1,0,1,0,1,0,1) (1,0,0,1,0,1,0,1) (1,1,0,0,0,0,1,0) (1,1,0,0,1,0,0,1) (1,1,1,0,0,1,0,1) (1,1,0,0,0,0,0,0)
C1 a
+ 0 + + 0 0 0 0 0 0 0 + 0 0 +
C2 a
+ 0 0 0 + 0 + + 0 + -
C4 a
0 0 0 + + + + 0 + 0 0 0 0
C3 a
0 0 0 0 0 + 0 + 0 0 + +,-,0 indicates charging, discharging and no effect of capacitor for postive direction of current.
C1 = Vdc/2 Capacitor, C2 = Vdc/4 Capacitor, C3 = Vdc/8 Capacitor, C1 = Vdc/16 Capacitor DESE, Indian Institute of Science Bangalore
Redundant states for pole voltage of V DC /16 (0,0,0,0,0,0,0,1) AC4 discharge DESE, Indian Institute of Science Bangalore
Redundant states for pole voltage of V DC /16 (0,0,0,0,0,0,0,1) AC4 discharge (0,0,0,0,0,1,1,0) AC3 discharge, AC4 charge DESE, Indian Institute of Science Bangalore
Redundant states for pole voltage of V DC /16 (0,0,0,0,0,0,0,1) AC4 discharge (0,0,0,1,1,0,1,0) AC2 dischargeAC3 charge, AC4 charge DESE, Indian Institute of Science Bangalore (0,0,0,0,0,1,1,0) AC3 discharge, AC4 charge
Redundant states for pole voltage of V DC /16 (0,0,0,0,0,0,0,1) AC4 discharge (0,0,0,0,0,1,1,0) AC3 discharge, AC4 charge (0,0,0,1,1,0,1,0) AC2 dischargeAC3 charge, AC4 charge DESE, Indian Institute of Science Bangalore (0,1,1,0,1,0,1,0) AC1 discharge, AC2 charge AC3 charge, AC4 charge
Redundant states for pole voltage of V DC /16 (0,0,0,0,0,0,0,1) AC4 discharge (0,0,0,0,0,1,1,0) AC3 discharge, AC4 charge (0,0,0,1,1,0,1,0) AC2 dischargeAC3 charge, AC4 charge DESE, Indian Institute of Science Bangalore (0,1,1,0,1,0,1,0) AC1 discharge, AC2 charge AC3 charge, AC4 charge (1,0,1,0,1,0,1,0) AC1 Charge, AC2 charge AC3 charge, AC4 charge
Capacitor balancing for pole voltage of V DC /16 (0,0,0,0,0,0,0,1) AC4 discharge (0,0,0,0,0,1,1,0) AC3 discharge, AC4 charge (0,0,0,1,1,0,1,0) AC2 dischargeAC3 charge,AC4 Charge (0,1,1,0,1,0,1,0) AC1 discharge, AC2 charge AC3 charge, AC4 charge (1,0,1,0,1,0,1,0) AC1 Charge, AC2 charge AC3 charge, AC4 charge DESE, Indian Institute of Science Bangalore
Space Vector States Each phase can generate 17 pole voltage levels.
Three phases can have total of 17 3 = 4913 combinations Voltage Space vector is given by V SV = V AO + V BO ∟120 o + V CO ∟240 o …(1) (V AO , V BO , V CO are three pole voltages) Each space vector can be generated in one or more pole voltage combinations.
Each pole voltage can have switching state redundancies.
DESE, Indian Institute of Science Bangalore
Experimental Verification Controller Block Diagram The proposed converter is implemented Semikron SKM75GB12T4 IGBT modules.
The switching frequency is set to 1KHz (2us dead time).
Controller was realized using TMS320F2812 DSP along with SPARTAN-3 XC3S200 FPGA to generate all the 48 PWM signals. All the capacitor voltage levels are sensed and compared with reference values using hysteresis comparator 3-Phase Y-connected 400V, 50Hz, SCIM is run in open loop V/f algorithm.
DESE, Indian Institute of Science Bangalore
Pole and Phase voltage at 10Hz operation VAC1( 50V/div), VAO: Pole voltage( 100V/div), VAN: Phase Voltage (100V/div), IA: 2A/div, Timescale: (20mS/div).
VAC4: (100V/div), VAC3: (10V/div), VAC2: (25V/div), IA:5A/div, Timescale: (20 mS/div).
DESE, Indian Institute of Science Bangalore
Pole and Phase voltage at 20Hz operation VAC1: ( 50V/div), VAO: Pole voltage( 100V/div), VAN: Phase Voltage (100V/div), IA: 2A/div, Timescale: (10mS/div).
VAC4: (20V/div), VAC3: (10V/div), VAC2: (25V/div), IA:2A/div, Timescale: 10mS/div DESE, Indian Institute of Science Bangalore
Pole and Phase voltage at 30Hz operation VAC1: ( 50V/div), VAO: Pole voltage( 100V/div), VAN: Phase Voltage (100V/div), IA: 2A/div, Timescale: (10mS/div).
VAC4: (20V/div), VAC3: (10V/div), VAC2: (25V/div), IA:2A/div, Timescale: 10mS/div DESE, Indian Institute of Science Bangalore
Pole and Phase voltage at 40Hz operation VAC1: ( 50V/div), VAO: Pole voltage( 100V/div), VAN: Phase Voltage (100V/div), IA: 2A/div, Timescale: (10mS/div) VAC4: (10V/div), VAC3: (10V/div), VAC2: (100V/div), Timescale: 5mS/div IA:2A/div, DESE, Indian Institute of Science Bangalore
Acceleration Profile VAC1:Cap AC1 voltage(100V/div), VAO: Pole Voltage(100V/div) , VAN: Phase Voltage(100V/div), IA: Phase current(2A/div) Timescale (500mS/div) VAC4:Cap AC4 voltage(10V/div), VAC3:Cap AC3 voltage (20V/div), VAC2:Cap AC2 voltage (20V/div), IA: Phase current(2A/div) Timescale (500mS/div) DESE, Indian Institute of Science Bangalore
Salient Features The proposed configuration uses single DC bus and generates the other voltage levels through capacitor balancing.
Use of single supply enables back to back converter topologies.
Proposed configuration has total of 48 devices.
Proposed configuration has total of 12 Capacitors.
Important feature is fault tolerant reliable operation at full load. If one of H-Bridges fail, the inverter can still be operated at full load by bypassing the faulty h bridge and operating the inverter at reduced number of levels.
DESE, Indian Institute of Science Bangalore
Part IV
A Hybrid Multilevel Converter scheme with Five Level Grid-Tied Active Front-end Feeding Seventeen-Level Multi level Inverter Induction Motor Drive
DESE, Indian Institute of Science Bangalore
Power Schematic of proposed grid tied inverter Block diagram of the proposed Back to back connected grid-tied inverter is shown above.
The Five-level inverter proposed in the part I has been used to run the active front end.
The seventeen level inverter proposed in part III has been used to run the motor side inverter.
DESE, Indian Institute of Science Bangalore
Phasor Diagrams of Active Front-end Random Power Factor Unity Power Factor Lagging Unity Power Factor Leading DESE, Indian Institute of Science Bangalore
Equations for Inductor Design Applying KVL across the grid and inverter at fundamental frequency Vi = Vg +L di/dt DESE, Indian Institute of Science Bangalore
Phasor Diagrams of Active Front-end
I L
Vgrid V Inductor =
jwL I L
V Inverter Limits of Components V inverter Max = 0.866 Vdc and (Vinverter) 2 = (Vinductor) 2 + (Vgrid) 2 Sets the limit on maximum inductance DESE, Indian Institute of Science Bangalore
Block Diagram of the Controller DESE, Indian Institute of Science Bangalore
Block Diagram of the PLL to generate angle DESE, Indian Institute of Science Bangalore
Schematic of 17-level inverter DESE, Indian Institute of Science Bangalore
Experimental Verification The proposed Active front-end converter is implemented Semikron SKM75GB12T4 IGBT modules.
The switching frequency is set to 1KHz (2us dead time).
Controller was realized using two sets of TMS320F2812 DSP along with SPARTAN-3 XC3S200 FPGA to generate all the PWM signals for both active front-end and motor side inverter. A three phase transformer is connected to isolate the converter from load and to step down the voltage.
All the capacitor voltage levels are sensed and compared with reference values using hysteresis comparator.
3-Phase Y-connected 400V, 50Hz, SCIM is run in open loop V/f algorithm.
DESE, Indian Institute of Science Bangalore
Grid and Motor Phase voltage at 10Hz operation Grid and motor phase voltages and currents at 10Hz operation.
VUO:Grid phase Voltage(250V/div) , IU:Grid Current(2A/div),VAN: Motor Phase Voltage(50V/div) and IA: Motor Phase current(5A/div) (Time scale:25mS/div) DESE, Indian Institute of Science Bangalore
Grid and Motor Phase voltage at 20Hz operation Grid and motor phase voltages and currents at 20Hz operation.
VUO:Grid phase Voltage(250V/div) , IU:Grid Current(2A/div),VAN: Motor Phase Voltage(50V/div) and IA: Motor Phase current(5A/div) (Time scale:10mS/div) DESE, Indian Institute of Science Bangalore
Grid and Motor Phase voltage at 30Hz operation Grid and motor phase voltages and currents at 30Hz operation.
VUO:Grid phase Voltage(250V/div) , IU:Grid Current(2A/div),VAN: Motor Phase Voltage(50V/div) and IA: Motor Phase current(5A/div) (Time scale:10mS/div) DESE, Indian Institute of Science Bangalore
Grid and Motor Phase voltage at 40Hz operation Grid and motor phase voltages and currents at 40Hz operation.
VUO:Grid phase Voltage(250V/div) , IU:Grid Current(2A/div),VAN: Motor Phase Voltage(50V/div) and IA: Motor Phase current(5A/div) (Time scale:5mS/div) DESE, Indian Institute of Science Bangalore
Transients During Sudden Acceleration Grid and motor phase voltages and currents during sudden acceleration at no load. IU:Grid Current(2A/div),VAN: Motor Phase Voltage(50V/div) and IA: Motor Phase current(5A/div) (Time scale:5mS/div) DESE, Indian Institute of Science Bangalore
Transients During Sudden Braking Grid and motor phase voltages and currents during sudden acceleration at no load. IU:Grid Current(2A/div),VAN: Motor Phase Voltage(50V/div) and IA: Motor Phase current(5A/div) (Time scale:5mS/div) DESE, Indian Institute of Science Bangalore
Regeneration Operation Regeneration operation of the grid tied inverter. VUN: Grid Phase Voltage (200V/div), IU: Grid Phase Current (5A/div), VAN: Motor Phase Volt age(200V/div). IA: Motor Phase Current(2A/div) Time scale:10mS/div DESE, Indian Institute of Science Bangalore
Conclusion The proposed configuration uses single DC bus and generates the other voltage levels through capacitor balancing both on grid side and motor side.
Important feature is fault tolerant reliable operation at full load. If one of H-Bridges fail, the inverter can still be operated at full load by bypassing the faulty h bridge and operating the inverter at reduced number of levels.
DESE, Indian Institute of Science Bangalore
Overview and Future Scope A new genre of converters using single DC link formed by cascading flying capacitor with floating capacitor H-bridges have been explored.
These converters use single DC link and generate all the required voltage levels from it.
These converters generate the output voltage levels faithfully irrespective of load power factor and direction of load current.
These converters can generate voltages of lower levels incase of failure of any of the H bridges and drive the load at full power. This enables this converter to be used for high reliability applications like marine and traction drives.
DESE, Indian Institute of Science Bangalore
Thank you
DESE, Indian Institute of Science Bangalore