Transcript An Introduction to Engineering Systems and Computing (2nd
ENG6530/ENG3050 Reconfigurable Computing Systems
General Information
Handout Winter 2014, January 6 th
Shawki Areibi
Office, Email, Phone
• Office: 2335, EXT 53819 • Email: [email protected]
• Web: http://www.uoguelph.ca/~sareibi • Office Hour: Thursday 2:00 – 3:00 PhD, Waterloo 1995
Research Interests
2 • VLSI Physical Design Automation (CAD/EDA) • Combinatorial Optimization (Heuristics/Meta-heuristics) • Reconfigurable Computing Systems/Embedded Systems RCS - Winter 2014 2
Outline
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Staff (TA, Lab Tech) Lecture Schedule Course Text and References Resources and Communication Assignments, Paper Review, Project Evaluation Course contents, Tentative Schedule
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Lab Coordinator
4 • Nate Groendyk • Lab#1 2307, Office 2308, ext 53873 • Lab#2 RICH 1532 • Email: [email protected]
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Teaching Assistant
5 • Ahmed Al-Wattar, PhD Student • Research: Reconfigurable Computing • TA for ENG2410, 2011, 2012, 2013 • Room THORN 2319, ext. 56493 • Email: [email protected]
• Office Hour: Wed 3:30 – 4:30 RCS - Winter 2014 5
Lecture Schedule
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Lectures
10:00 – 11:30 (Mon/Wed) In MACN 118
Starting Next Lecture
RICH 2531
Lab
3:30 – 5:30 (Monday) In RICH 1532 6 RCS - Winter 2014
Text Book and References
7 Text Books & References 1.
“Reconfigurable Computing: The Theory and Practice of FPGA-Based Computing”, Edited by S. Hauck, 2008.
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“Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications”, by C.Bobda
“Reconfigurable Computing: Accelerating Computation with FPGAs”, by Maya Gokhale “Computer Organization and Design”, by Patterson and Hennessy “VHDL for Engineers”, by K. Short, 2009.
“The Designer’s Guide to VHDL”, by Peter Ashenden 7 RCS - Winter 2014
Resources & Communication
8 http://www.uoguelph.ca/~sareibi 1.
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Communications E-mail ENG6530/ENG3050 Web Pages Username: Password: RCS - Winter 2014 8
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Prerequisites
Digital Design (ENG2410) Computer Organization (ENG3380) Basic knowledge of programming languages (C, C++) Basic Knowledge of Hardware Description Languages (VHDL) Experience in VLSI Design maybe helpful but not required.
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Course Objectives
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Achieves the following goals: Gives an overview of the traditional
Computer Von Neumann
Architecture, its specifications, design and implementations and main drawbacks. Techniques to improve the performance.
Teaches you the internal structure of
Programmable Logic
in general and Field Programmable Gate Arrays in particular.
Teaches you how digital circuits are designed today using advanced systems (
CAD tools and HDLs
Teaches you the basic concepts of Reconfigurable Computing
Hardware/Software
Teaches you and high level languages.
co-design)
when/how to apply
Reconfigurable Computing Concepts to design efficient, reliable, robust systems (DSP).
Understand the concept of Run Time Reconfiguration.
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Evaluation “Graduate”
11 Topic Assignments Paper Review Project Final Exam Weight 20% 10% 30% 40% RCS - Winter 2014 Details Assignments See Web Page See Web Page Closed Book Exam 11
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Evaluation “UnderGraduate”
Topic Assignments Paper Review Labs Final Exam Weight 20% 10% 20% 50% RCS - Winter 2014 Details Assignments See Web Page See Web Page Closed Book Exam 12
Paper Review
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Each student (group) is assigned several articles from journal papers/conferences.
Prepare a brief (20 minute) oral presentation of the article or topic (objectives, methods, results, contributions e.t.c.)
A Two page summary giving the citation and the material in the oral presentation must be written and a copy is distributed to each class member.
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Paper Review: Topics
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Coarse Grained Reconfigurable Arrays Evolvable Hardware Floating Point vs. Fixed Point representations CAD for RCS (High Level Synthesis) Operating Systems for Reconfigurable Computing Electronic System Level: A comparison ASICs vs. FPGAs vs. ASIPs Run Time Reconfiguration: Challenges Others …
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Research Project
“Graduate Students” will select a topic related to Reconfigurable Computing Systems.
You should conduct an in-depth study covering the problem to be solved and its current status.
Your finding should be documented in a report
Introduction to the problem
Motivation
Background Literature Review
Methodology Results
Conclusion
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What is Reconfigurable Computing?
Mapping algorithms traditionally running on general purpose processors onto reconfigurable platforms to achieve better performance.
Computation using hardware that can adapt at the logic level to solve specific problems Why is this interesting/important?
Some applications are poorly suited to General microprocessors.
16 VLSI “explosion” provides increasing resources.
Hardware/Software Co-design is main trend in Embedded Systems.
Accelerate scientific/industrial applications to achieve speedup (Real Time performance is necessary!) 16 RCS - Winter 2014
Microprocessor-based Systems Von-Neumann Architecture
Data Storage (Register File) A B C 17 ALU 64
Characteristics?
Generalized to perform many functions well.
Operates on fixed data sizes.
Instruction fetch, decode, execute Inherently sequential.
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Reconfigurable Computing
A B 18 } If (A > B) { H = A; L = B; } Else { H = B; L = A; Functional H Unit L Create specialized hardware for each application.
Functional units optimized to perform a special task. 18 RCS - Winter 2014
Implementation Spectrum
Microprocessor Reconfigurable Hardware ASIC
Characteristics?
19 ASIC gives high performance but is inflexible and expensive Processor is very flexible but not tuned to the application.
Reconfigurable hardware is a nice compromise.
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Tentative Schedule
Topic #1, Introduction to RCS Topic #2, Programmable Logic Devices Topic #3, CAD for RCS (FPGAs) Topic #4, VHDL Topic #5, High Level Languages (Handel-C) Topic #6, Reconfigurable Processors (ASIPs) Topic #7, Hardware/Software Co-design Topic #8, Run Time Reconfigurations Topic #9, Digital Signal Processing, Tools Topic #10, Design Exploration Techniques Topic #11, RCS Applications RCS - Winter 2014 20
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Topic #1: RCS, Introduction
Identify bottlenecks currently found in traditional Von Neumann Architectures. Learn new techniques to improve performance.
How/Why RCS can fill the gap between ASICs and General Purpose Processors.
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Topic #1, Cont ..: Technology Comparison
22 Technology Performance GPP LOW PDSP ASIC Medium HIGH Cost LOW Power HIGH Medium HIGH Medium LOW Flexibility HIGH Memory BW I/O BW LOW LOW Medium LOW Medium HIGH LOW HIGH FPGA Med-High LOWt Low-Medium HIGH RCS - Winter 2014 HIGH HIGH 22
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Topic #2: Programmable Logic
Programmable Or Array Programmable AND array Programmable AND array
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Programmable Or Array
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Topic #2 Cont … : FPGAs
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Around the beginning of the 1980s, it became apparent that there was a gap in the digital IC continuum.
At one end, there were programmable devices liks SPLDs and CPLDs, which were highly configurable but could not support large designs.
At the other end of the spectrum were ASICs which can support complex functions but were expensive, time consuming, … .
PLDs
SPLDs CPLDs
ASICs
The GAP Gate Arrays Structured ASICs* Standard Cell Full Custom RCS - Winter 2014 *Not available circa early 1980s 24
Topic #3: CAD for Programmable Logic
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Topic #3: FPGA Design Flow
Design Specification Design Entry/RTL Coding Behavioral or Structural Description of Design MEM LE I/O RTL Simulation
• Functional Simulation • Verify Logic Model & Data Flow (No Timing Delays) • •
Synthesis Translate Design into Device Specific Primitives Optimization to Meet Required Area & Performance Constraints
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Place & Route Map Primitives to Specific Locations inside
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Target Technology with Reference to Area & Performance Constraints Specify Routing Resources to Be Used
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Topic #4: VHDL
External Interface A B
circuit
Internal Functionality
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Outputs 27
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Topic #4: Synthesizable VHDL
VHDL for Specification VHDL for Simulation VHDL for Synthesis VHDL for Synthesis of Arithmetic Circuits
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Topic #5: Managing Complexity ESL
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Topic #5: High Level Languages
Take an algorithm written in C.
Generate an efficient hardware design, run it on an FPGA.
Fast design cycle, easy to maintain code.
C programmers should be able to create fast hardware!
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Topic #6: ASIPs
31 An ASIP is a stored memory CPU whose architecture is tailored for a particular set of applications.
The instruction-sets tailored to specific applications or application domains RCS - Winter 2014 31
Topic #7: Hardware/Software Co-design
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Interface process (a, b, c) in port a, b; out port c; { read(a); … write(c); } Specification Capture Model Partition Synthesize Line () { a = … … detach } Processor FPGA
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Topic #8: RTR
FPGAs are classified as dynamically reconfigurable if their embedded configuration storage circuitry and corresponding functions can be updated without disturbing the operation of the remaining logic.
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Topic #8, Cont ..: Virtual Hardware
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The concept of Run Time Reconfiguration on FPGAs is similar to the concept of Virtual Memory on Computer Systems.
Configuration data stored in memory device Function A Unused resources Active tasks Inactive tasks Function A Function B Function B Function C Overwrite function B with new function C RCS - Winter 2014 34
Topic#9: DSP
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Topic #9: DSP, Performance Gap
Algorithmic complexity increases as application demands increase.
In order to process these new algorithms, higher performance signal processing engines are required
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Topic #10: Design Exploration
Given an application (software implementation): what is the most appropriate hardware components and communication links that should be used?
The main challenge in DSE arises from the sheer size of the design space that must be explored.
Typically, a large system has millions, if not billions, of possibilities, and so enumerating every point in the design space is prohibitive.
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Topic #11: Applications
What applications require Hardware Acceleration?
Image processing, medical applications, real time … Hardware Accelerators for CAD Hardware Accelerators for ANNs Hardware Accelerators for Communication Systems RCS - Winter 2014 38
Satellite Imaging
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Satellite imaging used for mapping, environmental studies and defense applications High-data rate and low-power demands of space require cutting-edge technology such as RC to provide required processing capabilities Including RC devices in the processing chain will eventually enhance performance
c/o US Air Force
Receive Cube Pulse Compression Doppler Processing Space-Time Adaptive Processing (STAP)
c/o LANL
Constant False Alarm Rate (CFAR) Corner Turn GMTI processing chain Partitioned along range dimension
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Partitioned along pulse dimension
c/o LANL
Send Results
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fMRI and Real-time Human Body Imaging
Technique for determining which parts of the brain are activated by different types of physical sensation or activity – “brain mapping” High- and low-resolution scans compared using numerous FFTs
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Typically post-processed Much error correction needed due to subject movement 3D data representation requires a good deal of conventional processing Studying how RC devices can achieve real-time processing
Figures c/o University of Oxford, UK
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