Transcript Chapter # 4: Programmable and Steering Logic Contemporary

Chapter # 4: Programmable and
Steering Logic
No. 4-1
Chapter Overview
 PALs and PLAs
array logic
 Non-Gate Logic
Switch Logic
Multiplexers/Selecters and Decoders
Tri-State Gates/Open Collector Gates
ROM
 Combinational Logic Design Problems
Seven Segment Display Decoder
Process Line Controller
Logical Function Unit
Barrel Shifter
No. 4-2
PALs and PLAs
Pre-fabricated building block of many AND/OR gates (or NOR, NAND)
"Personalized" by making or breaking connections among the gates
(general purpose logic building blocks)
Programmable Array Block Diagram for Sum of Products Form
Inputs
Dense array of
AND gates
Product
terms
Dense array of
OR gates
Outputs
Ex. typical TTL FPLA with 16 inputs, 48 product terms, and 8 outputs
= 48 16-input AND and 8 48-input OR gates
No. 4-3
PALs and PLAs
Key to Success: Shared Product Terms
Equations
Example:
F0 = A + B' C'
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
Personality Matrix
Product
term
AB
BC
AC
BC
A
Inputs
A B C
1 1 - 0 1
1 - 0
- 0 0
1 - -
Outputs
F0 F1 F2 F3
0 1 1 0
0 0 0 1
0 1 0 0
1 0 1 0
1 0 0 1
Input Side:
1 = asserted in term
0 = negated in term
- = does not participate
Output Side:
1 = term connected to output
Reuse
0 = no connection to output
of
terms
No. 4-4
PALs and PLAs
Example Continued
All possible connections are available
before programming
No. 4-5
PALs and PLAs
Example Continued
Unwanted connections are "blown“
(after programming)
Note: some array structures
work by making connections
rather than breaking them
No. 4-6
PALs and PLAs
Alternative representation for high fan-in structures
Short-hand notation
so we don't have to
draw all the wires!
Notation for implementing
F0 = A B + A' B'
F1 = C D' + C' D
No. 4-7
PALs and PLAs
Design Example
Multiple functions of A, B, C
F1 = A B C
F2 = A + B + C
F3 = A B C
F4 = A + B + C
F5 = A xor B xor C
F6 = A xnor B xnor C
No. 4-8
PALs and PLAs
What is difference between Programmable Array Logic (PAL) and
Programmable Logic Array (PLA)?
PAL concept - implemented by Monolithic Memories
constrained topology of the OR Array (limited programmability)
A given column of the OR array
has access to only a subset of
the possible product terms
Product terms cannot be shared !
PLA concept - generalized topologies in AND and OR planes
For example in p. 4-9, PLA needs 14 product terms
while PAL needs 16 product terms
PLA achieves higher flexibility at the cost of lower speed!
No. 4-9
PALs and PLAs
Design Example: BCD to Gray Code Converter
Truth Table
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
W
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
X
0
0
0
0
1
1
0
0
0
0
X
X
X
X
X
X
K-maps
Y
0
0
1
1
1
1
1
1
0
0
X
X
X
X
X
X
Z
0
1
1
0
0
0
0
1
1
0
X
X
X
X
X
X
A
AB
00
01
11
10
00
0
0
X
1
01
0
1
X
1
11
0
1
X
X
10
0
1
X
X
CD
A
AB
00
01
11
10
00
0
1
X
0
01
0
1
X
0
11
0
0
X
X
10
0
0
X
X
CD
D
C
D
C
B
B
K-map for W
K-map for X
A
AB
00
01
11
10
00
0
1
X
0
01
0
1
X
0
CD
A
AB
00
01
11
10
00
0
0
X
1
01
1
0
X
0
CD
Minimized Functions:
W=A+BD+BC
X = B C'
C
Y=B+C
Z = A'B'C'D + B C D + A D' + B' C D'
D
11
1
1
X
D
X
11
0
1
X
X
10
1
0
X
X
C
10
1
1
X
X
B
B
K-map for Y
K-map for Z
No. 4-10
PALs and PLAs
Design Example: BCD to Gray Code Converter
Truth Table
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
W
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
X
0
0
0
0
1
1
0
0
0
0
X
X
X
X
X
X
K-maps
Y
0
0
1
1
1
1
1
1
0
0
X
X
X
X
X
X
Z
0
1
1
0
0
0
0
1
1
0
X
X
X
X
X
X
A
AB
00
01
11
10
00
0
0
X
1
01
0
1
X
1
11
0
1
X
X
10
0
1
X
X
CD
A
AB
00
01
11
10
00
0
1
X
0
01
0
1
X
0
11
0
0
X
X
10
0
0
X
X
CD
D
C
D
C
B
B
K-map for W
K-map for X
A
AB
00
01
11
10
00
0
1
X
0
01
0
1
X
0
CD
A
AB
00
01
11
10
00
0
0
X
1
01
1
0
X
0
CD
Minimized Functions:
W=A+BD+BC
X = B C'
C
Y=B+C
Z = A'B'C'D + B C D + A D' + B' C D'
PAL or PLA ???
D
11
1
1
X
D
X
11
0
1
X
X
10
1
0
X
X
C
10
1
1
X
X
B
B
K-map for Y
K-map for Z
No. 4-11
PALs and PLAs
Programmed PAL:
4 product terms per each OR gate
No. 4-12
PALs and PLAs
Code Converter Discrete Gate Implementation
A
\A
1
B
D
2
B
C
3
\A
\B
\C
D
W
B
C
D
2
3
4 4
A
D
B
C
22
1
1
1
X
\C
B
2
1
\B
Y
4
Z
5
\D
\B
C
\D
1:
2,5:
3:
4:
3
7404
7400
7410
7420
hex inverters
quad 2-i nput NAND
tri 3-input NAND
dual 4-input NAND
5 SSI Packages vs. 1 PLA/PAL Package!
No. 4-13
PALs and PLAs
Another Example: Magnitude Comparator
A
AB
00
01
11
10
00
1
0
0
0
01
0
1
0
0
CD
A
AB
00
01
11
10
00
0
1
1
1
01
1
0
1
1
CD
D
11
0
0
1
D
0
C
11
1
1
0
1
10
1
1
1
0
C
10
0
0
0
1
B
B
K-map for EQ
K-map for NE
A
AB
00
01
11
10
00
0
0
0
0
01
1
0
0
0
11
1
1
0
1
CD
A
AB
00
01
11
10
00
0
1
1
1
01
0
0
1
1
11
0
0
0
0
10
0
0
1
0
CD
D
C
D
C
10
1
1
0
0
B
B
K-map for LT
K-map for GT
No. 4-14
Non-Gate Logic
Introduction
AND-OR-Invert
PAL/PLA
Generalized Building Blocks
Beyond Simple Gates
Kinds of "Non-gate logic":
 switching circuits built from CMOS transmission gates, ROMs
 multiplexer/selecter functions
 decoders
 tri-state and open collector gates
 read-only memories
No. 4-15
Steering Logic
Voltage Controlled Switches
Gat e
Source
Drain
nMOS Transistor
Logic 1 on gate,
Source and Drain connected
Normally open switch
Gat e
Source
Drain
Logic 0 on gate,
Source and Drain connected
Normally closed switch
pMOS Transistor
No. 4-16
Steering Logic
CMOS Transmission Gate
nMOS transistors good at passing 0's but bad at passing 1's
pMOS transistors good at passing 1's but bad at passing 0's
perfect "transmission" gate places these in parallel:
Steering logic circuit – route data inputs to outputs based on the
settings of control signals. Ex) selector fun or mux
Control
Control
In
Out
Control
Switches
In
Control
Out
Control
Transistors
In
Out
Control
Transmission or
"Butterfly" Gate
No. 4-17
Steering Logic
Selection Function/Demultiplexer Function with Transmission Gates
S
Selector:
Choose I0 if S = 0
Choose I1 if S = 1
I
0
S
I
Z
S
1
S
S
Demultiplexer:
I to Z0 if S = 0
I to Z1 if S = 1
Z0
I
S
S
Z1
S
No. 4-18
Steering Logic
Use of Multiplexer/Demultiplexer in Digital Systems
A
Demultiplexers
Y
Multiplexers
B
Z
A
Y
Demultiplexers
B
Multiplexers
Z
So far, we've only seen point-to-point connections among gates
Mux/Demux used to implement multiple source/multiple destination
interconnect
No. 4-19
Steering Logic
Well-formed Switching Networks
Problem with the Demux implementation:
multiple outputs, but only one connected to the input!
S
Z0
S
"0"
I
S
S
Z1
S
"0"
S
The fix: additional logic to drive every output to a known value
(steer ‘0’ to Z0 or Z1)
Never allow outputs to "float"
No. 4-20
Steering Logic
Complex Steering Logic Example
N Input Tally Circuit: count # of 1's in the inputs
I
0
1
I1
1
Zero
One
I1
Straight Through
1
0
0
1
I1
"0"
Zer o
One
"0"
One
"1"
Zero
Diagonal
"0"
One
Conventional Logic
for 1 Input Tally
Function
"1"
Zero
"0"
Switch Logic Implementation
of Tally Function
No. 4-21
Steering Logic
Complex Steering Logic Example
Operation of the 1 Input Tally Circuit
"0"
"0"
One
"0"
"0"
One
"1"
Zero
"0"
"1"
Zero
"0"
Input is 0, straight through switches enabled
No. 4-22
Steering Logic
Complex Steering Logic Example
Operation of 1 input Tally Circuit
N inputs, N+1 outputs, count the number of inputs ‘1’
"1"
"0"
"1"
One
Zero
"1"
"0"
One
"1"
Zero
"0"
"0"
Input = 1, diagonal switches enabled
I1=1 (asserted)
No. 4-23
Steering Logic
Complex Steering Logic Example
Extension to the 2-input case
I 1 I2
0
0
1
1
0
1
0
1
Zero
1
0
0
0
One Two
0
1
1
0
0
0
0
1
I1
I2
Zero
One
Two
Conventional logic implementation
No. 4-24
Steering Logic
Complex Steering Logic Example
Switch Logic Implementation: 2-input Tally Circuit
Cascade the 1-input implementation!
No. 4-25
Steering Logic
Complex Steering Logic Example
Operation of 2-input implementation
No. 4-26
Complexity Comparison
• Switching networks still looks more complicated!
• But …
• Switching networks uses 24 transistors
– 2 inverters and 10 transmission gates
• Gate method uses 26 transistors
– Two-input NOR gate = 4 transistors
– AND gate = an inverter and a two-input NAND = 6 transistors
– XOR gate = four interconnected two-input NAND gates = 16
transistors
• Switching networks becomes a better choice for a
three- and four-input Tally circuit
No. 4-27
Multiplexers/Selectors
Use of Multiplexers/Selectors
Multi-point connections
A0
Sa
A1
B0
B1
MUX
MUX
A
B
Multiple input sources
Sb
Sum
Ss
DEMUX
S0
Multiple output destinations
S1
No. 4-28
Multiplexers/Selectors
General Concept
2
n
data inputs, n control inputs, 1 output
n
used to connect 2 points to a single point
control signal pattern form binary index of input connected to output
Z = A' I 0 + A I 1
A
0
1
Functional form
Logical form
Z
I0
I1
I1
0
0
0
0
1
1
1
1
I0
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
Z
0
0
1
0
0
1
1
1
Two alternative forms
for a 2:1 Mux Truth Table
No. 4-29
Multiplexers/Selectors
I0
2:1
mux
I1
Z = A' I 0 + A I 1
Z
A
I0
I1
I2
I3
4:1
mux
A
I0
I1
I2
I3
Z
B
8:1
mux
I4
I5
I6
Z
I7
A
Z = A' B' I0 + A' B I1 + A B' I2 + A B I3
B
C
Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 +
A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7
n -1
2
In general, Z = S
m I
k=0
k k
in minterm shorthand form for a 2 n :1 Mux
No. 4-30
Multiplexers/Selectors
Alternative Implementations
Gate Level
Implementation
of 4:1 Mux
thirty six transistors
Transmission Gate
Implementation of
4:1 Mux
twenty transistors
No. 4-31
Multiplexer/Selector
Large multiplexers can be implemented by cascaded smaller ones
I0
I1
I2
I3
0 4:1
1 mux
2
3 S1 S0
I4
I5
I6
I7
0 4:1
1 mux
2
3 S1 S0
B
Control signals B and C simultaneously
choose one of I0-I3 and I4-I7
8:1
mux
0 2:1
mux
1 S
Z
Control signal A chooses which of the
upper or lower MUX's output to gate to Z
I0
0
I1
1 S
C
C
A
I2
0
I3
1 S
0
1
Alternative 8:1 Mux Implementation
C
I4
0
I5
1 S
Z
2
3 S0
C
I6
0
I7
1 S
A
S1
B
C
No. 4-32
Multiplexer/Selector
Multiplexers/selectors as a general purpose logic block
n-1
2
:1 multiplexer can implement any function of n variables
n-1 control variables; remaining variable is a data input to the mux
Example:
F(A,B,C) = m0 + m2 + m6 + m7
= A' B' C' + A' B C' + A B C' + A B C
= A' B' (C') + A' B (C') + A B' (0) + A B (1)
1
0
1
0
0
0
1
1
0
1
2
3
4
5
6
7
F
8:1
MUX
S2 S1 S0
A
B
C
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F
1
0
1
0
0
0
1
1
C
C
0
C
C
0
1
0
1
2
3
4:1
MUX
S1
A
F
S0
B
1
"Lookup Table"
No. 4-33
Multiplexer/Selector
Generalization
I 1 I 2 ..
n-1 Mux
control variables
single Mux
data variable
..
In
0
1
F
0
0
0
1
1
0
1
1
Four possible
configurations
of the truth table rows
0
In
In
1
Can be expressed as
a function of In, 0, 1
Example:
G(A,B,C,D) can be implemented by an 8:1 MUX:
K-map
Choose A,B,C
as control variables
Multiplexer
Implementation
TTL package efficient
May be gate inefficient
1
D
0
1
D
D
D
D
0
1
2
3
4
5
6
7
G
8:1
mux
S2
A
S1
B
S0
C
No. 4-34
Decoders/Demultiplexers
Decoder: single data input, n control inputs, 2
n
outputs
control inputs (called select S) represent Binary index of output to which
the input is connected
data input usually called "enable" (G)
1:2 Decoder:
O0 = G · S; O1 = G · S
2:4 Decoder:
O0 = G · S0 · S1
3:8 Decoder:
O0 = G · S0 · S1 · S2
O1 = G · S0 · S1 · S2
O2 = G · S0 · S1 · S2
O1 = G · S0 · S1
O3 = G · S0 · S1 · S2
O2 = G · S0 · S1
O4 = G · S0 · S1 · S2
O3 = G · S0 · S1
O5 = G · S0 · S1 · S2
O6 = G · S0 · S1 · S2
O7 = G · S0 · S1 · S2
No. 4-35
Decoders/Demultiplexers
Alternative Implementations
G
Output0
/G
Select
Output0
Select
Output1
Output1
1:2 Decoder, Active High Enable
1:2 Decoder, Active Low Enable
2:4 Decoder, Active High Enable
2:4 Decoder, Active Low Enable
No. 4-36
Decoders/Demultiplexers
Switch Logic Implementations
Select
Select
G
G
Output
Out put
Select
Select
0
Select
Select
0
"0"
Select
Output
Select
1
Select
Out put
1
Select
Naive, Incorrect Implementation
Select
All outputs not driven at all times
"0"
Select
Correct 1:2 Decoder Implementation
No. of transistors – 8 vs. 10 (with NOR gate implementation)
No. 4-37
Decoders/Demultiplexers
Switch Implementation of 2:4 Decoder
Select
G
0
Select
1
Out put
0
Operation of 2:4 Decoder
"0"
S0 = 0, S1 = 0
"0"
G
Out put
1
"0"
one straight thru path
three diagonal paths
"0"
G
Out put
2
"0"
"0"
G
Out put
3
"0"
"0"
No. 4-38
Decoder/Demultiplexer
Decoder as a Logic Building Block
Enb
3:8
dec
S2
A
S1
B
S0
0
1
2
3
4
5
6
7
ABC
ABC
ABC
ABC
ABC
ABC
Decoder Generates Appropriate
Minterm based on Control Signals
ABC
ABC
C
Example Function:
F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D' + A B C
F3 = (A' + B' + C' + D')
No. 4-39
Decoder/Demultiplexer
Decoder as a Logic Building Block
Enb
4:16
dec
S3 S2 S1 S0
A
B C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ABCD
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
AB C D
F1
F2
F3
D
If active low enable, then use NAND gates!
No. 4-40
Multiplexers/Decoders
Alternative Implementations of 32:1 Mux
I7
I6
I5
I4
I3
I2
I1
I0
C
D
E
EN
I31 7 151
EN 1 6
5
1
Y5
I23 7 151
41 4
6 5 3
W 6
EN 1 5
22
1
3
5
1
I15 7 151
41 4
40Y 6
1
52 3
W
EN 1 6
5
2
3
C
3 1 Y 19
1
5
7 151
4
4
B
4 0W 1 6A
6 51 3
22
5
9C 0
3 1 Y 15 B 1
4
40 1 6
13
W0 A
2
9
1
1 1 C
B
0 1A
S2 0
1
S1
S0
1 1G 1Y3
1391Y2
A 3 1B 1Y1
2 1A 1Y0
B
15 2G 2Y3
2Y2
13 2B 2Y1
14 2A 2Y0
1 GA
3 A3
4 A2
5 A1
6 A0
13
12
11
10
1
5
153
YA 7 F(A, B, C, D, E)
B3
B2
YB 9
B1
B0
GBS1 SO
Multiplexer Only –
8:1 MUX + 4:1 MUX
2 14
A B
7
6
5
4
9
10
11
12
7 EN 146
5
154
I31 7 151
6 13
7 EN
I5 145 2 2
154 3 1 Y 5
I23 7 I4151
3 40
7 EN 146 I3 1
6
I5 5 I2 2 2 9 CW
15
3
5B
I15 7 I4151
4 I1 1 Y 10
3 I0 4 0 W 116A
7 EN 146 I3 1
2
I5 5 I2 2 C 9 C
S2
154 I1 31Y 10
5B
I7 7 I4 151
S1
I6 6 I3 1 3 I0 40WD 116A
I5 5 I2 2 2 C 9C
S2E S0
5
I4 4 I1 3 1 Y 10
S1
D 11B
I3 3 I0 4 0 W
6A
I2 2 C 9 C
S2E S0
I1 1 10B
S1
I0 0 D 11A
C S2E S0
D S1
E S0
F(A, B, C, D, E)
Multiplexer + Decoder –
2:4 decoder + 8:1 MUX
No. 4-41
Multiplexers/Decoders
5:32 Decoder
\EN
S4
S3
\EN
1G
1Y3
139 1Y2
1B 1Y1
1A 1Y0
2G 2Y3
2Y2
2B 2Y1
2A 2Y0
S2
S1
S0
Y7
Y6
Y5
Y4
138 Y3
Y2
C
Y1
B
Y0
A
\Y31
\Y30
\Y29
\Y28
\Y27
\Y26
\Y25
\Y24
Y7
Y6
Y5
138 Y4
Y3
Y2
C
Y1
B
Y0
A
\Y23
\Y22
\Y21
\Y20
\Y19
\Y18
\Y17
\Y16
Y7
Y6
Y5
138 Y4
Y3
C
Y2
B
Y1
A
Y0
\Y15
\Y14
\Y13
\Y12
\Y11
\Y10
\Y9
\Y8
G1 Y7
G2A Y6
G2B Y5
138 Y4
Y3
Y2
C
Y1
B
Y0
A
\Y7
\Y6
\Y5
\Y4
\Y3
\Y2
\Y1
\Y0
G1
G2A
G2B
\Y31
5:32
Decoder
Subsystem
G1
G2A
G2B
.
.
.
S2
S1
S0
\Y0
S4 S3 S2 S1 S0
G1
G2A
G2B
S2
S1
S0
S2
S1
S0
No. 4-42
Tri-State and Open-Collector
The Third State
Logic States: "0", "1"
Don't Care/Don't Know State: "X" (must be some value in real circuit!)
Third State: "Z" - high impedance - infinite resistance, no connection
Tri-state gates: output values are "0", "1", and "Z"
additional input: output enable (OE)
A OE F
X 0 Z
0 1 0
1 1 1
When OE is high, this gate is a non-inverting "buffer"
When OE is low, it is as though the gate was
disconnected from the output!
This allows more than one gate to be connected to the
same output wire, as long as only one has its
output enabled at the same time
100
Non-inverting buffer's
timing waveform
A
OE
F
"Z"
"Z"
No. 4-43
Tri-state and Open Collector
Using tri-state gates to implement an economical multiplexer:
Input 0
F
OE
When SelectInput is asserted high
Input1 is connected to F
Input 1
OE
When SelectInput is driven low
Input0 is connected to F
This is essentially a 2:1 Mux
Selec tInput
If F=Input1 (OE=1), Input2 is in high
Impedance.
No. 4-44
Tri-state and Open Collector
Alternative Tri-state Fragment
F
Input 0
Active low tri-state enables
plus inverting tri-state buffers
OE
Input 1
pMOS
or normally closed switch
1
OE
Selec tInput
F
I
OE
Switch Level Implementation
of tri-state gate for inverting buffer
0
nMOS or normally open switch
No. 4-45
Tri-State and Open Collector
4:1 Multiplexer, Revisited
\EN
S1
S0
1
1G 1Y3
1Y2
3 139
1B 1Y1
2
1A 1Y0
15
7
6
5
4
D3
9
2G 2Y3 10
2Y2
13 2B
2Y1 11
14 2A
2Y0 12
D2
D1
D0
Decoder + 4 tri-state Gates
No. 4-46
Tri-State and Open Collector
Open Collector
another way to connect multiple gates to the same output wire
gate only has the ability to pull its output low; it cannot actively
drive the wire high
this is done by pulling the wire up to a logic 1 voltage through a
resistor
+5 V
Pull -up res istor
Open-collector
NAND gate
F
0V
A
B
OC NAND gates
Wired AND:
If A and B are "1", output is actively pulled low
if C and D are "1", output is actively pulled low
if one gate is low, the other high, then low wins
if both gates are "1", the output floats, pulled
high by resistor
Hence, the two NAND functions are AND'd (wired)
together!
No. 4-47
Tri-State and Open Collector
4:1 Multiplexer
\EN 1
Y3
G
139 Y2
3
Y1
B
S1
2
Y0
A
S0
+5V
7
6
5
4
\I3
OR
\I2
OR
\I1
OR
\I0
OR
F
Decoder + 4 Open Collector Gates
No. 4-48
Read-Only Memories
ROM: Two dimensional array of 1's and 0's
Row is called a "word"; index is called an "address"
Width of row is called bit-width or wordsize
Address is input, selected word is output
+5V +5V +5V +5V
n
2 -1
De c
i
W ord Line 0011
j
W ord Line 1010
0
0
n-1
Addr e s s
Bit Lines
Internal Organization
No. 4-49
Read-Only Memories
Example: Combination Logic Implementation
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
Address
ROM
8 words ¥by
4 bi ts
A B C
addres s
F0
F1
F2
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F0
0
1
0
0
1
1
0
0
F1
0
1
1
0
0
0
0
1
F2
1
1
0
0
1
0
0
0
F3
0
0
0
1
1
0
1
0
Word Contents
F3
outputs
No. 4-50
Read-Only Memories
Memory array
Not unlike a PLA
structure with a
fully decoded
AND array!
Dec oder
2n word
li nes
n address
li nes
2n words by
m bits
m output
li nes
ROM vs. PLA:
ROM approach advantageous when
(1) design time is short (no need to minimize output functions)
(2) most input combinations are needed (e.g., code converters)
(3) little sharing of product terms among output functions
ROM problem: size doubles for each additional input, can't use don't cares
PLA approach advantageous when
(1) design tool like espresso is available
(2) there are relatively few unique minterm combinations
(3) many minterms are shared among the output functions
PAL problem: constrained fan-ins on OR planes
No. 4-51
Read-Only Memories
+
2764 EPROM
8K x 8
2764
VPP
PGM
A12
A11
A10
O7
A9
O6
A8
O5
A7
O4
A6
O3
A5
O2
A4
O1
A3
O0
A2
A1
A0
CS
OE
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U3
OE
A13
/OE
A12:A0
D15:D8
D7:D0
+
16K x 16
Subsystem
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U1
OE
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U2
OE
+
+
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U0
OE
No. 4-52
Combinational Logic Word Problems
General Design Procedure
1. Understand the Problem
what is the circuit supposed to do?
write down inputs (data, control) and outputs
draw block diagram or other picture
2. Formulate the Problem in terms of a truth table or other suitable
design representation
truth table or waveform diagram
3. Choose Implementation Target
ROM, PAL, PLA, Mux, Decoder + OR, Discrete Gates
4. Follow Implementation Procedure
K-maps, espresso, misII
No. 4-53
Combinational Logic Word Problems
Process Line Control Problem
Statement of the Problem
Rods of varying length (+/-10%) travel on conveyor belt
Mechanical arm pushes rods within spec (+/-5%) to one side
Second arm pushes rods too long to other side
Rods too short stay on belt
3 light barriers (light source + photocell) as sensors
Design combinational logic to activate the arms
Understanding the Problem
Inputs are three sensors, outputs are two arm control signals
Assume sensor reads "1" when tripped, "0" otherwise
Call sensors A, B, C
Draw a picture!
No. 4-54
Combinational Logic Word Problems
Process Control Problem
+10%
+ 5%
+ 5%
Spec
Spec
Spec
- 5%
- 5%
- 10%
ROD
Too
Long
ROD
W it hin
Spec
ROD
Too
Short
Where to place the light sensors A, B, and C to distinguish among
the three cases?
Assume that A detects the leading edge of the rod on the conveyor
No. 4-55
Combinational Logic Word Problems
Process Control Problem
A
Too
Long
W it hin
Spec
Too
Short
Spect ification
- 5%
Specificat ion
+ 5%
B
C
A to B distance place apart at specification - 5%
A to C distance placed apart at specification +5%
No. 4-56
Combinational Logic Word Problems
Process Control Problem
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Function
X
X
X
X
too short
X
in spec
too long
Truth table and logic implementation
now straightforward
"too long" = A B C
(all three sensors tripped)
"in spec" = A B C'
(first two sensors tripped)
No. 4-57
Combinational Logic Word Problems
BCD to 7 Segment Display Controller
Understanding the problem:
input is a 4 bit bcd digit
output is the control signals for the display
4 inputs A, B, C, D
7 outputs C0 - C6
C0 C1 C2 C3 C4 C5 C6
C0
C5
C6
C4
7-Segment
display
C1
C2
C3
BCD-to-7-s egment
c ontrol s ignal
dec oder
C C C C C C C
0 1 2 3 4 5 6
A
B
C
D
Block Diagram
No. 4-58
Combinational Logic Word Problems
BCD to 7 Segment Display Controller
Formulate the problem in terms of a
truth table
Choose implementation target:
if ROM, we are done
don't cares imply PAL/PLA may be
attractive
Follow implementation procedure:
hand reduced K-maps
vs.
espresso
No. 4-59
Combinational Logic Word Problems
BCD to 7 Segment Display Controller
A
AB
00
01
11
10
00
1
0
X
1
01
0
1
X
1
CD
A
AB
00
01
11
10
00
1
1
X
1
01
1
0
X
1
CD
D
11
1
1
X
11
1
1
X
1
1
X
X
00
1
1
X
1
01
1
1
X
1
11
1
1
X
X
10
0
1
X
X
C
10
1
0
X
X
B
K-map for C0
K-map for C1
K-map for C2
A
A
AB
01
11
10
00
1
0
X
1
01
0
1
X
0
11
1
0
X
X
00
01
11
10
00
1
0
X
1
01
0
0
X
0
11
0
0
X
X
CD
C
X
X
00
01
11
10
00
1
1
X
1
01
0
1
X
1
11
0
0
X
X
10
0
1
X
X
CD
1
1
X
X
00
01
11
10
00
0
1
X
1
01
0
1
X
1
11
1
0
X
X
10
1
1
X
X
CD
D
D
C
10
A
AB
D
C
1
A
AB
D
1
10
B
00
10
11
B
AB
CD
01
D
X
C
10
00
CD
D
X
C
A
AB
C
B
B
B
B
K-map for C3
K-map for C4
K-map for C5
K-map for C6
C0 = A + B D + C + B' D'
C1 = A + C' D' + C D + B'
C2 = A + B + C' + D
C3 = B' D' + C D' + B C' D + B' C
C4 = B' D' + C D
C5 = A + C' D' + B D' + B C'
C6 = A + C D' + B C' + B' C
No. 4-60
Combinational Logic Word Problems
BCD to 7 Segment Display Controller
A
AB
00
01
11
10
00
1
0
X
1
01
0
1
X
1
CD
A
AB
00
01
11
10
00
1
1
X
1
01
1
0
X
1
CD
D
11
1
1
X
11
1
1
X
1
1
X
X
00
1
1
X
1
01
1
1
X
1
11
1
1
X
X
10
0
1
X
X
C
10
1
0
X
X
B
K-map for C0
K-map for C1
K-map for C2
A
A
AB
01
11
10
00
1
0
X
1
01
0
1
X
0
11
1
0
X
X
00
01
11
10
00
1
0
X
1
01
0
0
X
0
11
0
0
X
X
CD
C
X
X
00
01
11
10
00
1
1
X
1
01
0
1
X
1
11
0
0
X
X
10
0
1
X
X
CD
1
1
X
X
00
01
11
10
00
0
1
X
1
01
0
1
X
1
11
1
0
X
X
10
1
1
X
X
CD
D
D
C
10
A
AB
D
C
1
A
AB
D
1
10
B
00
10
11
B
AB
CD
01
D
X
C
10
00
CD
D
X
C
A
AB
C
B
B
B
B
K-map for C3
K-map for C4
K-map for C5
K-map for C6
C0 = A + B D + C + B' D'
C1 = A + C' D' + C D + B'
C2 = A + B + C' + D
15 Unique Product Terms
C3 = B' D' + C D' + B C' D + B' C
C4 = B' D' + C D
C5 = A + C' D' + B D' + B C'
C6 = A + C D' + B C' + B' C
No. 4-61
Combinational Logic Word Problems
BCD to 7 Segment
Display Controller
In cre me nt
1
0
Fi rst
fu se
nu mb ers
4
8
12
16
20
24
28
0
32
64
96
12 8
16 0
19 2
22 4
19
25 6
28 8
32 0
35 2
38 4
41 6
44 8
48 0
18
51 2
54 4
57 6
60 8
64 0
67 2
70 4
73 6
17
76 8
80 0
83 2
86 4
89 6
92 8
96 0
99 2
16
10 24
10 56
10 88
11 20
11 52
11 84
12 16
12 48
15
12 80
13 12
13 44
13 76
14 08
14 40
14 72
15 04
14
15 36
15 68
16 00
16 32
16 64
16 96
17 28
17 60
13
17 92
18 24
18 56
18 88
19 20
19 52
19 84
20 16
12
2
3
16H8PAL
(programming map)
can Implement
the function
10 external inputs,
6 feedback inputs,
8 outputs,
7 product terms / output
4
5
6
7
8
9
11
N ote: Fu se numbe r = firs t fu se n umbe r + inc remen t
No. 4-62
Combinational Logic Word Problems
BCD to 7 Segment
Display Controller
In cre me nt
012 3
4
8
10
12
14
16
18
20
24
27
1
2
Fi rst
fu se
nu mb ers
14H8PAL
Cannot Implement
the function
23
0
28
56
84
22
1
11 2
14 0
21
16 8
19 6
20
22 4
25 2
19
28 0
30 8
18
33 6
36 4
17
39 2
42 0
16
44 8
47 6
50 4
53 2
15
3
4
5
14 inputs,
8 outputs,
2 outputs w/ 4 product
terms OR’ed
6 outputs w/ 2 product
terms OR’ed
6
7
8
9
10
14
11
13
N ote: Fu se numbe r = firs t fus e n umber + in cr eme nt
No. 4-63
Combinational Logic Word Problems
BCD to7 Segment Display Controller
.i 4
.o 7
.ilb a b c d
.ob c0 c1 c2 c3 c4 c5 c6
.p 16
0000 1111110
0001 0110000
0010 1101101
0011 1111001
0100 0110011
0101 1011011
0110 1011111
0111 1110000
1000 1111111
1001 1110011
1010 ------1011 ------1100 ------1101 ------1110 ------1111 ------.e
.i 4
.o 7
.ilb a b c d
.ob c0 c1 c2 c3 c4 c5 c6
.p 9
-10- 0000001
-01- 0001001
C0
-0-1 0110000
-101 1011010
C1
--00 0110010
C2
--11 1110000
C3
-0-0 1101100
C4
1--- 1000011
-110 1011111
C5
.e
C6
espresso
output
= B C' D + C D + B' D' + B C D' + A
= B' D + C' D' + C D + B' D'
= B' D + B C' D + C' D' + C D + B C D'
= B C' D + B' D + B' D' + B C D'
= B' D' + B C D'
= B C' D + C' D' + A + B C D'
= B' C + B C' + B C D' + A
9 Unique Product Terms-great sharing
of terms! (it was 15)
espresso
input
No. 4-64
Combinational Logic Word Problems
BCD to 7 Segment Display Controller
PLA Implementation
No. 4-65
Combinational Logic Word Problems
BCD to7 Segment Display Controller
Multilevel Implementation via misII
X = C' + D'
Slowest output
Y = B' C'
C0 = C3 + A' B X' + A D Y
C1 = Y + A' C5' + C' D' C6
C2 = C5 + A' B' D + A' C D
C3 = C4 + B D C5 + A' B' X'
52 literals
33 gates
Ineffective use of don't cares
C4 = D' Y + A' C D'
C5 = C' C4 + A Y + A' B X
C6 = A C4 + C C5 + C4' C5 + A' B' C
No. 4-66
Combinational Logic Word Problems
Logical Function Unit
Statement of the Problem:
3 control inputs: C0, C1, C2
2 data inputs: A, B
1 output: F
No. 4-67
Combinational Logic Word Problems
Logical Function Unit
Formulate as a truth table
Choose implementation technology
5-variable K-map
espresso
multiplexor implementation
A
B
4 TTL packages:
4 x 2-input NAND
4 x 2-input NOR
2 x 2-input XOR
8:1 MUX
A
B
A
B
+
5
V
DD D D D D D D S
01 2 3 4 5 6 7 0
S
E
1
N
Q
S
O
2
C2
C1
C0
F
No. 4-68
Combinational Logic Word Problems
Logical Function Unit
Follow implementation procedure (K map)
C1 C2
AB
00
C0=0 00 1
01
11
10
1
1
1
1
11
1
10
1
1
1
F = C2' A' B' + C0' A B'
+ C0' A' B + C1' A B
5 gates, 5 inverters
1
C1 C2
AB
00
C0=1 00 1
1
01
1
11
10
1
Three packages:
1 x three 3-input NAND
1 x two 4-input NAND
1 x 6 inverters
Alternative: 32 x 1-bit ROM
01
11
01
1
1
single package
10
No. 4-69
Combinational Logic Word Problems
8-Input Barrel Shifter
Specification:
Inputs: D7, D6, …, D0
Outputs: O7, O6, …, O0
Control: S2, S1, S0
shift input the specified number
of positions to the left
Understand the problem:
D7
D6
D5
D4
D3
D2
D1
D0
.
.
.
O7
O6
O5
O4
O3
O2
O1
O0
S2, S1, S0 = 0 0 0
D7
D6
D5
D4
D3
D2
D1
D0
.
.
.
O7
O6
O5
O4
O3
O2
O1
O0
S2, S1, S0 = 0 0 1
D7
D6
D5
D4
D3
D2
D1
D0
.
.
.
O7
O6
O5
O4
O3
O2
O1
O0
S2, S1, S0 = 0 1 0
No. 4-70
Combinational Logic Word Problems
8-Input Barrel Shifter
Function Table
Boolean
equations
S2 S1 S0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
O7
D7
D6
D5
D4
D3
D2
D1
D0
O6
D6
D5
D4
D3
D2
D1
D0
D7
O5
D5
D4
D3
D2
D1
D0
D7
D6
O4
D4
D3
D2
D1
D0
D7
D6
D5
O3
D3
D2
D1
D0
D7
D6
D5
D4
O2
D2
D1
D0
D7
D6
D5
D4
D3
O1
D1
D0
D7
D6
D5
D4
D3
D2
O0
D0
D7
D6
D5
D4
D3
D2
D1
O7 = S2' S1' S0' D7 + S2' S1' S0 D6 + .. + S2 S1 S0 D0
O6 = S2' S1' S0' D6 + S2' S1' S0 D5 + .. + S2 S1 S0 D7
O5 = S2' S1' S0' D5 + S2' S1' S0 D4 + .. + S2 S1 S0 D6
O4 = S2' S1' S0' D4 + S2' S1' S0 D3 + .. + S2 S1 S0 D5
O3 = S2' S1' S0' D3 + S2' S1' S0 D2 + .. + S2 S1 S0 D4
O2 = S2' S1' S0' D2 + S2' S1' S0 D1 + .. + S2 S1 S0 D3
O1 = S2' S1' S0' D1 + S2' S1' S0 D0 + .. + S2 S1 S0 D2
O0 = S2' S1' S0' D0 + S2' S1' S0 D7 + .. + S2 S1 S0 D1
No. 4-71
Different approaches
• Discrete gate approach
– No simplification possible
– 8 4-input gates and one 8-input gate per function
– 40 packages: 32 for 4-input gates and 8 for 8-input gates
• MSI component approach
– 8:1 MUX per function
– Only 8 packages
• Single package approach
– ROM: 2048 (2^11) by 8 bit words due to 11 inputs
– PAL: 11 inputs, 8 outputs, and 8 product terms / OR gate output
• Switching network approach
– Natural approach since shift is easily done with steering logic!
– Possible to implement with 64 transistors: most efficient
No. 4-72
Combinational Logic Word Problems
8-Input Barrel Shifter
Via switch logic & 3:8 decoder
S000
O7
O6
O5
O4
O3
O2
O1
O0
S000
O6
O5
O4
O3
O2
O1
O0
D7
D7
S001
D6
O7
S001
S001
D6
S010
S001
S010
D5
D5
S011
D4
S011
D4
D3
S100
D3
S100
S101
D2
S110
D1
S111
D0
D2
D1
D0
Crosspoint switches
S101
S110
S111
Fully Wired crosspoint switch
No. 4-73
Chapter Review
 Non-Simple Gate Logic Building Blocks:
PALs/PLAs
Multiplexers/Selecters
Decoders
ROMs
Tri-state, Open Collector
 Combinational Word Problems:
Understand the Problem
Formulate in terms of a Truth Table
Choose implementation technology
Implement by following the design procedure
No. 4-74