Transcript Lecture 8 Memory Elements and Clocking

Lecture 10
Registers, Counters and Shifters
Prith Banerjee
ECE C03
Advanced Digital Design
Spring 1998
ECE C03 Lecture 10
1
Outline
•
•
•
•
•
•
Registers
Register Files
Counters
Designs of Counters with various FFs
Shifters
READING: Katz 7.1, 7.2, 7.4, 7.5, 4.7 Dewey
10.2, 10.3, 10.4, Hennessy-Patterson B26
ECE C03 Lecture 10
2
Building Complex Memory Elements
• Flipflops: most primitive "packaged" sequential circuits
• More complex sequential building blocks:
Storage registers, Shift registers, Counters
Available as components in the TTL Catalog
• How to represent and design simple sequential circuits: counters
• Problems and pitfalls when working with counters:
Start-up States
Asynchronous vs. Synchronous logic
ECE C03 Lecture 10
3
Registers
• Storage unit. Can hold an n-bit value
• Composed of a group of n flip-flops
– Each flip-flop stores 1 bit of information
• Normally use D flip-flops
D
Q
Dff
clk
D
Q
Dff
clk
D
Q
Dff
clk
D
Q
Dff
clk C03 Lecture 10
ECE
4
Controlled Register
Reset
0
1
0
Load
0
0
1
Action
Q = old Q
Q=0
Q=D
D
Q
Dff
clk
D
Q
Dff
clk
D
Q
Dff
clk
D
Q
Dff
clk
ECE C03 Lecture 10
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Registers
Group of storage elements read/written as a unit
4-bit register constructed from 4 D FFs
Shared clock and clear lines
Schematic Shape
171
12 CLK
13 CLR
11
5
4
14
D3
D2
D1
D0
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
9
10
7
6
2
3
1
15
TTL 74171 Quad D-type FF with Clear
(Small numbers represent pin #s on package)
ECE C03 Lecture 10
6
Variations of Registers
Selective Load Capability
Tri-state or Open Collector Outputs
True and Complementary Outputs
377
11
1
18
17
14
13
8
7
4
3
CLK
EN
D7
D6
D5
D4
D3
D2
D1
D0
374
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
11
18
17
14
13
8
7
4
3
19
16
15
12
9
6
5
2
74377 Octal D-type FFs
with input enable
EN enabled low and
lo-to-hi clock transition
to load new data into
register
CLK
H
QH
G QG
F
QF
E
QE
D
QD
C
QC
B
QB
A
QA
OE
1
19
16
15
12
9
6
5
2
74374 Octal D-type FFs
with output enable
OE asserted low
presents FF state to
output pins; otherwise
high impedence
ECE C03 Lecture 10
7
Register Files
Two dimensional array of flipflops
Address used as index to a particular word
Word contents read or written
670
11
4
5
12
13
14
3
2
1
15
Separate Read and Write Enables
Separate Read and Write Address
Data Input, Q Outputs
RE
RB
RA
WE
WB
WA
D4
D3
D2
D1
Q4
Q3
Q2
Q1
Contains 16 D-ffs, organized as
four rows (words) of four elements (bits)
6
7
9
10
74670 4x4 Register File with
Tri-state Outputs
ECE C03 Lecture 10
8
Shift Registers
Storage + ability to circulate data among storage elements
\Reset
Shift Direction
Shift
J Q
K Q
J Q
K Q
J Q
K Q
J Q
K Q
Shift
Shift
Shift
\Reset
Q1
Q2
Q3
Q4
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
Shift
Shift from left storage
element to right neighbor
on every lo-to-hi transition
on shift signal
Q1
Q2
Q3
Q4
Wrap around from rightmost
element to leftmost element
Master Slave FFs: sample inputs while
clock is high; change outputs on
falling
edge
ECE C03 Lecture
10
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Shift Registers I/O
Serial vs. Parallel Inputs
Serial vs. Parallel Outputs
Shift Direction: Left vs. Right
QD
QC
QB
QA
74194 4-bit Universal
Shift Register
Serial Inputs: LSI, RSI
Parallel Inputs: D, C, B, A
Parallel Outputs: QD, QC, QB, QA
Clear Signal
Positive Edge Triggered Devices
S1,S0 determine the shift function
S1 = 1, S0 = 1: Load on rising clk edge
synchronous load
S1 = 1, S0 = 0: shift left on rising clk edge
LSI replaces element D
S1 = 0, S0 = 1: shift right on rising clk edge
RSI replaces element A
S1 = 0, S0 = 0: hold state
Multiplexing logic on input to each FF!
Shifters well suited for serial-to-parallel conversions,
ECE C03
Lecture 10
such as terminal
to computer
communications
10
Application of Shift Registers
Parallel to Serial Conversion
D7
D6
D5
D4
Clock
Parallel
Inputs
D3
D2
D1
D0
Sender
Receiver
S1
S0 194
LSI
D
QD
C
QC
B
QB
A
QA
RSI
CLK
CLR
S1
S0 194
LSI
D
QD
C
QC
B
QB
A
QA
RSI
CLK
CLR
D7
D6
D5
D4
S1
S0 194
LSI
D
QD
C
QC
B
QB
A
QA
RSI
CLK
CLR
S1
S0 194
LSI
D
QD
C
QC
B
QB
A
QA
RSI
CLK
CLR
D3
D2
D1
D0
Parallel
Outputs
Serial
transmission
ECE C03 Lecture 10
11
Counters
Proceed through a well-defined sequence of states in response to
count signal
3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...
3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...
Binary vs. BCD vs. Gray Code Counters
A counter is a "degenerate" finite state machine/sequential circuit
where the state is the only output
ECE C03 Lecture 10
12
Johnson Counters
+
1
0
+
+
\Reset
S
J
Q
CLK
K
Q
R
Q1
S
J
Q
CLK
K
Q
R
Q2
S
J
Q
CLK
K
Q
R
Q3
S
J
Q
CLK
K
Q
R
End-Around
Q4
Shift
+
100
Shift
Q1
1
1
1
1
0
0
0
0
Q2
0
1
1
1
1
0
0
0
Q3
0
0
1
1
1
1
0
0
Q4
0
0
0
1
1
1
1
0
8 possible states, single bit change
per state,
useful for avoiding glitches
ECE C03 Lecture
10
13
Catalog Counters
7 P
10 T 163
15
2 CLK RCO
6
5
4
3
D
C
B
A
9
LOAD
1
CLR
QD
QC
QB
QA
11
12
13
14
74163 Synchronous
4-Bit Upcounter
Synchronous Load and Clear Inputs
Positive Edge Triggered FFs
Parallel Load Data from D, C, B, A
P, T Enable Inputs: both must be asserted to
enable counting
RCO: asserted when counter enters its highest
state 1111, used for cascading counters
"Ripple Carry Output"
74161: similar in function, asynchronous load and reset
ECE C03 Lecture 10
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74163 Detailed Timing Diagram
CLR
LOAD
A
B
C
D
CLK
P
T
QA
QB
QC
QD
RCO
Clear
12
Load
13
14
15
0
1
ECE
Count C03 Lecture 10
2
Inhibit
15
Counter Design Procedure
This procedure can be generalized to implement ANY finite state
machine
Counters are a very simple way to start:
no decisions on what state to advance to next
current state is the output
Example: 3-bit Binary Upcounter
00
0
0
0
1
Present
State
C B A
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Next
State
Flipflop
Inputs
C+ B+ A+ TC TB TA
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
State Transition
Table
1
0
1
0
1
0
1
0
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
Flipflop
Input Table
ECE C03 Lecture 10
Decide to implement with
Toggle Flipflops
What inputs must be
presented to the T FFs
to get them to change
to the desired state bit?
This is called
"Remapping the Next
State Function"
16
Example Design of Counter
K-maps for Toggle
Inputs:
Resulting Logic Circuit:
CB
A
00
11
10
11
10
01
0
1
TA =
CB
A
00
01
0
1
TB =
CB
A
00
01
11
10
0
1
TC =
ECE C03 Lecture 10
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Resultant Circuit for Counter
K-maps for Toggle
Inputs:
+
C
CB
A
Resulting Logic Circuit:
00
01
11
10
0
1
1
1
1
1
1
1
1
1
TSQ
CLK Q
R
B
TA = 1
QA
T SQ
CLK Q
R
QB
QC
T SQ
CLK Q
R
\Reset
C
CB
00
01
11
10
0
0
0
0
0
1
1
1
1
1
A
B
TB = A
100
QC
00
01
11
10
0
0
0
0
0
1
0
1
1
0
A
Timing Diagram:
\Res et
C
CB
Count
QB
QA
Count
B
TC = A • B
ECE C03 Lecture 10
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More Complex Counter Design
Step 1: Derive the State Transition Diagram
Count sequence: 000, 010, 011, 101, 110
Present
State
Next
State
Step 2: State Transition Table
000
010
011
101
110
0
0
1
1
0
1
1
0
1
0
0
1
1
0
0
ECE C03 Lecture 10
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Complex Counter Design (Contd)
Step 1: Derive the State Transition Diagram
Count sequence: 000, 010, 011, 101, 110
Present
State
Next
State
Step 2: State Transition Table
000
001
010
011
100
101
110
111
0 1 0
XXX
0 1 1
1 0 1
XXX
1 1 0
0 0 0
XXX
Note the Don't Care conditions
ECE C03 Lecture 10
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Counter Design (Contd)
Step 3: K-Maps for Next State Functions
CB
A
00
01
11
CB
10
A
0
0
1
1
C+ =
00
01
11
10
B+ =
CB
A
00
01
11
10
0
1
A+ =
ECE C03 Lecture 10
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Counter Design (contd)
Step 4: Choose Flipflop Type for Implementation
Use Excitation Table to Remap Next State Functions
Q Q+
T
0
0
1
1
0
1
1
0
0
1
0
1
Toggle Excitation
Table
Present
State
Toggle
Inputs
CBA
TC TB TA
000
001
010
011
100
101
110
111
0 1 0
XXX
0 0 1
1 1 0
XXX
0 1 1
1 1 0
XXX
Remapped Next State
Functions
ECE C03 Lecture 10
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Resultant Counter Design
Remapped K-Maps
CB
A
00
01
11
CB
10
A
0
0
1
1
00
TC
01
11
10
TB
CB
A
00
01
11
10
0
1
TA
TC = A C + A C = A xor C
TB = A + B + C
TA = A B C + B C
ECE C03 Lecture 10
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Resultant Circuit for Complex Counter
Resulting Logic:
5 Gates
13 Input Literals +
Flipflop connections
TC
Count
T
S Q C
TB
CLK Q
\C
R
B
T S Q
CLK Q
\B
R
TA
A
T S Q
CLK Q
\A
R
\Reset
A
C
TC
A
\B
C
Timing Waveform:
TB
\A
B
C
\B
C
TA
100
Count
\Res et
C
0
0
0
0
1
1
0
B
0
0
1
1
0
1
0
A
0
0
1
0
0
ECE
0 C03 Lecture
1 10
24
Implementing Counters with Different FFs
• Different counters can be implemented best with
different counters
• Steps in building a counter
– Build state diagram
– Build state transition table
– Build next state K-map
• Implementing the next state function with
different FFs
• Toggle flip flops best for binary counters
• Existing CAD software for finite state machines
favor D FFs
ECE C03 Lecture 10
25
Implementing 5-state counter with RS FFs
Continuing with the 000, 010, 011, 101, 110,
000, ... counter example
Q Q+ R S
0
0
1
1
0
1
0
1
X
0
1
0
0
1
0
X
Q+ = S + R Q
RS Exitation Table
Present
State
000
001
010
011
100
101
110
111
Next
State
0 1 0
XXX
0 1 1
1 0 1
XXX
1 1 0
0 0 0
XXX
Rmepped next state
RC SC RB SB RA SA
X
X
X
0
X
0
1
X
0
X
0
1
X
X
0
X
0
X
0
1
X
0
1
X
1
X
X
0
X
1
0
X
X 0
X X
0 1
0 X
X X
1 0
X 0
X X
Remapped Next State Functions
ECE C03 Lecture 10
26
Implementation with RS FFs
RS FFs Continued
CB
A
CB
00
01
11
X
X
1
X
X
0
X
0
0
1
10
00
01
11
10
0
0
0
0
X
1
X
1
X
X
A
RC
CB
SC = A
CB
00
01
11
10
0
0
0
1
X
1
X
1
X
0
A
00
01
11
10
0
1
X
0
X
1
X
0
X
1
A
RB
0
1
01
X
X
0
0
RA
11
X
X
10
X
1
A
0
1
SB = B
SA = B C
CB
00
RB = A B + B C
RA = C
SB
CB
A
RC = A
SC
00
01
0
X
1
X
11
0
X
ECE C03 Lecture
SA 10
10
X
0
27
Implementation With RS FFs
\A
A
R
Q
CLK
Q
S
C
RB
R
Q
CLK
Q
S
\B
\C
Count
A
C
B
B
C
SA
R
Q
CLK
Q
S
\B
RB
A
\A
B
\C
SA
Resulting Logic Level Implementation:
3 Gates, 11 Input Literals + Flipflop connections
ECE C03 Lecture 10
28
Implementing with JK FFs
Continuing with the 000, 010, 011, 101, 110,
000, ... counter example
Q Q+ J
K
0
0
1
1
X
X
1
0
0
1
0
1
0
1
X
X
Q+ = S + R Q
RS Exitation Table
Present
State
000
001
010
011
100
101
110
111
Next
Rmepped next state
State JC KC JB KB JA KA
0 1 0
XXX
0 1 1
1 0 1
XXX
1 1 0
0 0 0
XXX
0
X
0
1
X
X
X
X
X
X
X
X
X
0
1
X
1
X
X
X
X
1
X
X
X
X
0
1
X
X
1
X
0 X
X X
1 X
X 0
X X
X 1
0 X
X X
Remapped Next State Functions
ECE C03 Lecture 10
29
Implementation with JK FFs
CB
A
CB
00
01
11
10
A
0
0
1
1
00
JC
11
10
JC = A
KC
CB
A
01
KC = A/
CB
00
01
11
10
A
00
01
11
10
0
0
JB = 1
1
1
KB = A + C
JB
CB
A
JA = B C/
KB
KA = C
CB
00
01
11
10
A
0
0
1
1
JA
00
01
11
10
KA
ECE C03 Lecture 10
30
Implementation with JK FFs
+
A
\A
J Q C
CLK
K Q
KB
\C
J Q B
CLK
K Q
\B
JA
C
J Q A
CLK
K Q
\A
Count
A
C
KB
B
\C
JA
Resulting Logic Level Implementation:
2 Gates, 10 Input Literals + Flipflop Connections
ECE C03 Lecture 10
31
Implementation with D FFs
Simplest Design Procedure: No remapping needed!
DC = A
DB = A C + B
DA = B C
A
D
Q
C
DB
CLK Q \ C
D
Q
B
CLK Q \ B
DA
D
Q
CLK Q
A
\A
Count
\C
\A
DB
\B
B
\C
DA
Resulting Logic Level Implementation:
3 Gates, 8 Input Literals + Flipflop connections
ECE C03 Lecture 10
32
Comparison with Different FF Types
• T FFs well suited for straightforward binary counters
But yielded worst gate and literal count for this example!
• No reason to choose R-S over J-K FFs: it is a proper subset of J-K
R-S FFs don't really exist anyway
J-K FFs yielded lowest gate count
Tend to yield best choice for packaged logic where gate count is key
• D FFs yield simplest design procedure
Best literal count
D storage devices very transistor efficient in VLSI
Best choice where area/literal count is the key
ECE C03 Lecture 10
33
Asynchronous vs. Synchronous Counters
Deceptively attractive alternative to synchronous design style
Ripple Counters
T
Q
T
Q
A
CLK Q
T
Q
B
CLK Q
C
CLK Q
Count
Count signal ripples from left to right
Count
Reset
A
B
C
State transitions are not sharp!
Can lead to "spiked outputs" from combinational logic
decoding the counter's state
ECE C03 Lecture 10
34
Power of Synchronous Clear and Load
Starting Offset Counters:
e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110, ...
100
D C B A
Cloc k
Load
1
6
3
P
+
R
Q Q QQ
C
D CBA
OC
L
T K DCBA
D
L
O C
A L
D R
C
B
A
+ Load 0 1
0110
is the state
to be loaded
Use RCO signal to trigger Load of a new state
Since 74163 Load is synchronous, state changes
only on the next rising clock edge
ECE C03 Lecture 10
35
Shifters
• We have discussed some core logic design circuits
for designing datapaths of computers
– adders
– ALUs
– multipliers
• A final component which is very important is a
shifter
– Takes a n-bit input and performs a shift left or right by
m bits
– Can define arithmetic shifts, logical shifts or circular
shifts, e.g. circular shift left
a7 a6 a5 a4 a3 a2 a1 a0
ECE C03 Lecture 10
a6 a5 a4 a3 a2 a1 a0 a7
36
8-input Barrel Shifter
Specification:
Inputs: D7, D6, …, D0
Outputs: O7, O6, …, O0
Control: S2, S1, S0
shift input the specified number
of positions to the right
Understand the problem:
D7
D6
D5
D4
D3
D2
D1
D0
.
.
.
O7
O6
O5
O4
O3
O2
O1
O0
S2, S1, S0 = 0 0 0
D7
D6
D5
D4
D3
D2
D1
D0
.
.
.
O7
O6
O5
O4
O3
O2
O1
O0
S2, S1, S0 = 0 0 1
ECE C03 Lecture 10
D7
D6
D5
D4
D3
D2
D1
D0
.
.
.
O7
O6
O5
O4
O3
O2
O1
O0
S2, S1, S0 = 0 1 0
37
Functional Description of Shifter
Function Table
Boolean
equations
S2 S1 S0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
O7
D7
D6
D5
D4
D3
D2
D1
D0
O6
D6
D5
D4
D3
D2
D1
D0
D7
O5
D5
D4
D3
D2
D1
D0
D7
D6
O4
D4
D3
D2
D1
D0
D7
D6
D5
O3
D3
D2
D1
D0
D7
D6
D5
D4
O2
D2
D1
D0
D7
D6
D5
D4
D3
O1
D1
D0
D7
D6
D5
D4
D3
D2
O0
D0
D7
D6
D5
D4
D3
D2
D1
O7 = S2' S1' S0' D7 + S2' S1' S0 D6 + … + S2 S1 S0 D0
O6 = S2' S1' S0' D6 + S2' S1' S0 D5 + … + S2 S1 S0 D7
O5 = S2' S1' S0' D5 + S2' S1' S0 D4 + … + S2 S1 S0 D6
O4 = S2' S1' S0' D4 + S2' S1' S0 D3 + … + S2 S1 S0 D5
O3 = S2' S1' S0' D3 + S2' S1' S0 D2 + … + S2 S1 S0 D4
O2 = S2' S1' S0' D2 + S2' S1' S0 D1 + … + S2 S1 S0 D3
O1 = S2' S1' S0' D1 + S2' S1' S0 D0 + … + S2 S1 S0 D2
10 S1' S0 D7 + … + S2 S1 S038D1
O0 = S2' S1' ECE
S0' C03
D0Lecture
+ S2'
8-input Barrel Shifter
• Straightforward gate level implementation
– Looking at the Boolean equations earlier it is not
possible to simplify them
• Discrete gate implementation would require
– eight 4-input AND gates and one 8-input OR gate per
outputfunction
– total 64 8-input AND gates, and 8 8-input OR gates for
8 output functions
– Requires 40 TTL SSI packages
ECE C03 Lecture 10
39
Alternative Implementations of Shifter
• Use MSI components such as multiplexers and
decoders
• Each output function can be implemented by an
8:1 multiplexer, need eight MUXex, eight
packages
• Use the control input S2 S1 S0 to control mux
D7
D6
…
D1
D0
O7
S2S1S0
D7
D6
…
D1
D0
O6
S2S1S0
ECE C03 Lecture 10
D7
D6
…
D1
D0
O0
S2S1S0
40
Shifter Design Using Switching Logic
•Remember that one can use CMOS transistors as switches
that turn on when the gate signal is high, and off when gate
signal is low
•Need 64 switches (transistors) plus a decoder in a regular design
S000
O7
O6
O5
O4
O3
O2
O1
O0
S000
O6
O5
O4
O3
O2
O1
O0
D7
D7
S001
D6
O7
S001
S001
D6
S010
S001
S010
D5
D5
S011
D4
S011
D4
D3
S100
D3
S100
S101
D2
S110
D1
S111
D0
D2
D1
D0
Crosspoint switches
S101
S110
S111
Fully Wired crosspoint switch
ECE C03 Lecture 10
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Summary
•
•
•
•
•
•
•
Registers
Register Files
Counters
Designs of Counters with various FFs
Shifters
NEXT LECTURE: Memory Design
READING: Katz 7.6
ECE C03 Lecture 10
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