SubWavelength IC Design and Manufacturing

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Transcript SubWavelength IC Design and Manufacturing

Numerical Technologies, Inc
4-13-99
Tutorial on Subwavelength
Lithography
DAC 99
Y. C. (Buno) Pati
Numerical Technologies, Inc.
DAC 99 June 24, 1999
Agenda
 Background
 The SubWavelength Gap
 SubWavelength Technologies




Optical proximity correction (OPC)
Phase shifting
Process modeling
Silicon Level Verification
 Some implications for physical design?
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DAC 99 June 24, 1999
Optical Lithography
 Image of circuit
patterns projected
onto wafer
 Feature size limited
by diffraction
effects
 Rayleigh limits

q
NA
Depth of focus
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Mask
Silicon Wafer
Resolution
R
Illumination
(Wavelength )
DOF 

NA2
Numerical Aperture:
NA  sin(q )
DAC 99 June 24, 1999
Mask Types
 Bright Field Masks
 Opaque features defined
by chrome
 Background is
transparent
 Used e.g. for poly, metal,
...
 Dark Field Masks
 Transparent features
defined
 Background is opaque
(chrome)
 Used e.g. for contacts, ...
Clear areas
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Opaque (chrome)
areas
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Next Generation Lithography
Technologies
 Extended UV EUV - 13nm wavelength
 x-rays
 Electron beams
 Common characteristics:
 At least 10 years away
 Requires significant research and development
 Requires major infrastructure changes
 More than 25 years of infrastructure and experience
supporting supporting optical lithography
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The SubWavelength™ Gap
Lithography Wavelength
Silicon Feature Size
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DAC 99 June 24, 1999
The Impact of SubWavelength
Lithography
LAYOUT
MASK
SILICON
WAFER
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Traditional (WSYIWYG) relationship between
layout, mask and silicon is no longer valid due
to process distortions, OPC, and phase
shifting
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Bridging the SubWavelength™ Gap
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DAC 99 June 24, 1999
Optical Proximity Correction (OPC)
 Corrective
modifications to
improve process
control
Conventional
(no OPC)
Silicon Image
w/o OPC
 improve yield
 improve device
performance
Original
Layout
0.18 mm
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OPC Layout
Silicon Image
with OPC
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Phase-Shifting (PSM) Technology
 Phase modulation
used at mask
level to
Gate lengths
reduced to 0.1 mm
Silicon Image
w/o PSM
PSM Layout
Silicon Image
with PSM
 reduce feature
size
 improve yield
 improve device
performance
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Original Layout
0.18 mm
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Light Source
Mask
Opaque
Transparent
180 o phase
shifter
Wafer
Without Phase Shifting
With Phase Shifting
0.11mm
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Insufficient image contrast to
successfully print silicon features
0.11 mm silicon features printed
using a 0.35 mm nominal process
Scanning Electron Micrograph (SEM)
courtesy Hewlett Packard
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 0.18 micron transistors
fabricated with a 0.18
micron process
0.18 mm
 0.09 micron transistors
fabricated with the same
0.18 micron process and
NTI phase shifting
technology
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SEM Courtesy Motorola
0.09 mm
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Optical Proximity Correction
 Goal: Improve device
performance and yield
 Cosmetic correction
complicates mask
manufacturing and
dramatically increases cost
with little benefit
 OPC is not new, it’s just
more complicated than it
was before
 Key issues:
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 Manufacturability
 Design and verification tools
OPC Features
 Serifs - for corner rounding
 Hammerheads - for line-end
shortening
 Assists - for CD control
 Biasing - for CD control
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Approaches to OPC
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Rule-Based OPC
Model-Based OPC
 Apply corrections based
on a set of predetermined rules
 Fast design time
 Lower mask complexity
 Suitable for less
“aggressive” designs
 Use process simulation
to determine corrections
on-line
 Longer design time
 Increased mask
complexity
 Suitable for
“aggressive” designs
DAC 99 June 24, 1999
Phase-Shifting - Background
 Proposed for lithography application in 1982 by Marc
Levenson (IBM)
 Heightened interest in early 90’s
 Near wavelength - no pressing need
 Infrastructure, i.e. design automation, mask manufacturing,
... not in place
 Many different forms of phase-shifting proposed
 Key issues:
 Manufacturability
 Design and verification tools
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Some Forms of Phase-Shifting Masks
0
 Bright Field Phase-Shifting
 Single exposure
 Phase transitions required e.g.
60, 120, 90, 270
 Throughput unaffected
 Limited improvement in
process latitude
 Mask manufacturing difficult
 Double exposure
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 PSM with 0 and 180 degree
phase shifters + binary trim
mask
 Excellent process latitude
 Decrease in throughput
90
270
120
180
60
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Gate Shrinking and CD Control
Using Phase Shifting
Binary Mask
(0.20 mm)
Prints
0.20 mm line
Original
Design
Prints
0.11 mm gates
+
+
Dark Field
PSM
Prints 0.11
mm lines
Poly
Active
180
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0
Phase
Shifters
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Image Formation Using Double Exposure
Phase Shifting
Chrome Mask
PSM
Combined
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DUV, NA=0.60, s 0.50
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Phase Shifting Improves Critical
Dimension (CD) Control
BIM (250 nm L/S )
PSM (150 nm L/ 300 nm S)
Line width contours shown for a full wafer (45 fields, 36 measurements per
field. Contour interval: 5nm. DUV, NA = 0.42, s = 0.5
(Joint work with Hua-Yu Liu*, HP ULSI Research Laboratories)
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* Now at Numerical Technologies
DAC 99 June 24, 1999
Wafer Dimension (mm)
Controlling Silicon Dimensions
Phase Shift vs. Binary
0.35
0.30
0.25
0.20
Series1
0.15
Series3
Binary
Phase
Series2
Shifting
0.10
0.05
180°
0.00
0.00
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DUV, NA=0.57,
s=0.40
0.05
0.10
0.15
0.20
Mask Dimension (mm)
0.25
0.30
0
°
X
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Design
FAB
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•Process
Optimization
•Design Rule
Generation
Inspection
and Repair
Equipment
Process Simulation
and Development
Tools
SubWavelength
Design Tools
SubWavelength
Inspection/Repair
SubWavelength
Process
Development
Subwavelength
•Mask Manufacturing
•Defect Inspection
•Repair
EDA Software
Tools
Production Process
•Physical Design
•Extraction
•Verification
Mask
SubWavelength Infrastructure
DAC 99 June 24, 1999
Phase-shifting Technology Impacts
Physical Layout
 Phase conflicts occur
when two objects with
minimum spacing
cannot be assigned
contrasting phase
 Layout designers must
ensure that layouts are
free of phase conflicts
 This is analogous to,
but not the same as
checking design rules
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180°
0°
Phase
Conflict
180°
180°
0°
180°
Conflict
Eliminated
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SubWavelength Design and Manufacturing Data Flow
Detailed Process Information Process Models... Phase Shift and OPC Design Rules... Tolerances...
 Silicon
Visualization
Custom Layout
 Phase
Conflicts
Place and
Route
 Phase
Conflicts
 Conflict
resolution
 Virtual
Mask
Stepper
Manufacturing
inspection
 Repair
Mask
 Si vs. Layout
 OPC
Verification  Si Image
Extraction
Physical Design
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 Detailed
Process
process
Development/
information
Wafer Fab
 PSM & OPC
Design rules
Wafer Fabrication
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Calibrated Process Simulation Models
Lithography Process
mask
process
layout
stepper
optics
photo
resist
etch
calibrated model
Process Model
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printed
pattern
simulated
printed
pattern
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Applications of Process Models
Process
Measurements
Process Model Calibrator
Calibrated
Process Model
Process Simulation
OPC
Phase Shifting
Inputs
PS & OPC Rule Generation
Silicon DRC
Si Image Extraction
Mask Inspection
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Outputs
DAC 99 June 24, 1999
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Silicon Verification - Silicon vs. Layout
Silicon Level
Verification
Physical
Verification
Design
Layout
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Layout - DRC

Silicon - DRC
X
Layout - LVS

Silicon - LVS
X
Layout - Timing

Silicon - Timing
X
Compares silicon to layout
Silicon level verification can catch silicon failures prior to
commiting to masks and silicon
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How does it work?
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Silicon image simulation checks against
target, and flags failures
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Summary
 SubWavelength technologies are critical to IC
manufacturing for the next 7-10 years
 OPC is a corrective technology
 Phase shifting is an enabling technology
 SubWavelength design and manufacturing requires
the coordinated interaction of physical design with
lithography process, semiconductor equipment, and
mask manufacturing
 Moore’s Law will live on (for now)! ….
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