Transcript Redundancy Techniques - IUMA

332:437 Lecture 12
Finite State Machine Design






Hardware design approach
Mealy and Moore Machines
Edge-Triggered Flip-Flops
State Machine Analysis
State Machine Synthesis
Summary
Material from An Engineering Approach to Digital Design, by
William I. Fletcher, Prentice-Hall Inc.
7/18/2015
Bushnell: Digital Systems
Design Lecture 12
1
Suggested Hardware Design
Approach
1.
2.
3.
4.
Break circuit design into multiple functional
blocks
Optimize each block into a 2-level or multi-level
logic form (K-map, Variable-entered map,
Synopsys, etc.)
Check for acceptable propagation delay in the
system, and go back to Steps 1 and 2 for
redesign, if necessary
Use a redundant logic identification to find
unnecessary logic and remove it
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Design Lecture 12
2
State Machine Design
Sequential logic, circuits, or machines:
1. Have internal memory
2. Types:
 Synchronous (clocked) – memory elements
controlled by an external signal – can change
only at specific times
 Asynchronous – less frequently used but
more interesting – memory elements change
state whenever 1 or more inputs change –
no clock
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State Machine Design
3.
4.
VERY IMPORTANT: Control conditions under
which state changes
 Otherwise single input change causes many
state changes, due to relative logic delays
Asynchronous Logic:
 Faster than synchronous for small circuits
 Slower than synchronous for large circuits
• REASON: Vastly more logic is required
due to absence of CLOCK
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Mealy Machines
Mealy Machine

X
Present
Inputs
St
Present
State
Output
Decoder
Circuit
Outputs (present)
Z
Z = f (X, St)
Next State
Decoder
Memory Devices
Or State
Next
State
St+1 = g (X, St)
Clock
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Moore Machines
Circuit
Outputs (present)
Present
Inputs
X
St
Present
State
Output
Decoder
Z = f (St)
Next State
Decoder
Memory Devices
Or State
Clock
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Z
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Design Lecture 12
Next
State
St+1 = g (X, St)
6
Mealy Machines
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
0
1
Nasty to design reliably and debug
WHY?
 Real circuits have hazards:
1 a
0 b
a
b
c


c0
0
hazard
Undesirable: You expect c to be 0, and run it as input to
a flip-flop which catches the short logic 1 pulse on c
(called one’s catching)
Flip-flop gets set, but you expected it to be cleared
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Hazards
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Unavoidable
Different signals have different propagation
delays
 Different paths through circuit
 Different logic gates have different delay
times – determined by:
1. Gate type
2. Number of inputs
Mealy machines do not filter out hazards, from
inputs to outputs
 WHY? Output decoder is a function of inputs
as well as of state
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Hazards Propagating Through
Output Decoder

Output decoder:
Xi
Sj t

Zk
Timing diagram:
Clock
Xi
Sjt
Zk
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Moore Machine
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Output is stable:
 Filters out hazards in primary outputs, since
they cannot propagate from inputs to outputs
Rule: Never design a Mealy Machine unless you
really have to
 Unfortunately, you often have to do it to
satisfy the circuit functional specification
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State Machine Design Process
1.
2.
3.
4.
5.
6.
7.
Identify State Variables S
Identify Output Decoder & Next State Decoder
Build State Transition Diagram
Minimize States
Choose appropriate type of flip-flops
Choose State Assignment
 Assignment of binary codes to machine
states
Design next state decoder & output decoder –
use combinational logic structured design
methods – K-maps, Variable-Entered Map,
Verilog
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Design Lecture 12
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Mealy Machine Sequence
Detector Recognizing 1102
Double circle shows reset state
1/0
0/0 S1 0/0 S2

1/0
0/1
X/Z
S3
Present Input X/Z
Present State
0
1
S1
S1/0
S2/0
S2
S1/0
S3/0
S3
S1/1
S3/0
1/0
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Moore Machine Sequence
Detector Recognizing 1102
Pay for better behavior of Moore machine with
extra flip-flop

S1/0
0
0
S4/1
1
0
S3/0
1
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Present Present
Input Output
1
0
S2/0
1
Present State
S1
S2
S3
S4
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Design Lecture 12
0
S1
S1
S4
S1
1
S2
S3
S3
S2
Z
0
0
0
1
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Flip-Flops
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Cross-coupled NOR/NAND latches
Clocked Master-Slave Flip-Flop (Pulse or
level-triggered)
/S
R
Q
00 for /R & /S
not allowed
Q
/R
Master latch
S
R
1
2
3
4
S
Q
Q
11 for R & S
not allowed
Slave latch
5
6
7
Q
8
Q
CP
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One’s Catching Problem
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Timing Diagram shows problem
Master starts oscillating
If too close to clock falling edge, Slave might
record a 0, not a 1
CP
S
R
Setup Hold
Enable
1&2
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Disable
1&2
Enable
5&6
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Design Lecture 12
Disable
5&6
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Edge-Triggered Flip-Flop


Sensitive only to input changes around rising
clock edge (positive edge-triggered)
 Setup and Hold times
 Less likely to catch a 0 or 1
Characteristic Table:
D Qt
Qt+1
0
0
0
1
0
0
0
1
1
1
1
1
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Edge-Triggered Flip-Flop State
Transition Diagram
C
1
Forces S & R
to 1
0
D=1
D=0
Forces B to 1
A to 0
C0
1
Forces S High
R Low
Resets FF
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Forces B to 0
A to 1
C0
1
Forces R High
S Low
Sets FF
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Edge-Triggered Flip-Flop Logic
Circuit
A
/S
Q
C
D
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/R
Q
B
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Sequential Circuit Analysis
1.
2.
3.
4.
5.
6.
7.
8.
Identify inputs (X’s), outputs (Z’s), coded states (Y’s)
Obtain output equations Z = F (X, Y)
Obtain Flip-Flop excitation equations Di = Gi (X, Y)
Construct Excitation Table from excitation equations for all
possible output states
Construct Next State Table from Excitation Table
Merge output functions to Next State Table
 Form Coded State Transition Table
Construct State Transition Table from Coded State
Transition Table
Construct State Transition Diagram
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Example – Mealy Machine
5
x
y2
y1
y2
x
y1
x
y1
1
J1 Q1
z
y1
C
2
K1 Q1
y1
3
J2 Q2
y2
C
4
K2 Q2
y2
CLK
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Analysis
1.
2.
3.
z is output
y1 and y2 are state variables – maximum of 4
states
X = [x = 0, x = 1]
Z = [z = 0, z = 1]
Y = [y1y2 = 00, 01, 10, 11]
Output Equations z = xy1
Flip-Flop Excitation Equations
J1 = x  y2
J2 = x y1
K1 = y1 + y2
K 2 = x  y1
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Analysis (continued)
4.
Evaluate J1, K1, J2, K2 under all possible inputs
 Flip-Flop Excitation Table
x
y1y2
00
01
11
10
0
00,01,0
11,01,0
11,10,0
01,10,0
1
10,10,0
01,10,0
01,11,1
11,11,1
J1K1,J2K2,z
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Analysis (continued)
5.
Apply JK FF Characteristic Table to Flip-Flop
Excitation Table to get Next State Table
x
y1y2
00
01
11
10
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0
00
10
01
01
1
11
01
00
01
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Analysis (continued)
6.
Create Coded State Transition Table
 Merge in Present Output
x/z
y1y2
00
01
11
10
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0
00/0
10/0
01/0
01/0
1
11/0
01/0
00/1
01/1
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Design Lecture 12
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Analysis (continued)
7.
Create State Transition Table
 Name the states – each distinct combination
of y1y2
x/z
y1y2 State
0
1
00 a
a/0
c/0
01 b
d/0
b/0
11
c
b/0
a/1
10 d
b/0
b/1
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Analysis (concluded)
8.
Use State Transition Table to create State Transition
Diagram
1/0
b
0/0
1/0
0/0
a
c
0/0
1/1
State b – recognized 10
d
1’s
1/1
0/0
01
O/P high
State a – recognized
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0’s
11
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State Machine Synthesis

1.
2.
3.
Same steps as analysis, but in reverse
Write accurate word description of the problem.
“Build a machine that will produce 1 on the
output z when 4+ consecutive 1’s occur on x
after at least one 0 input has occurred.”
Form State Transition Table
State Reduction
If 2 states a & b have same output sequence
when started in a & b for any input
sequence, they are equivalent states
 Outputs & next states must be same
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Synthesis (continued)
4.
Make state assignment
 Problems:
1. No known general procedure gives
minimal cost
2. Make all unused states transition to idle
state under all input conditions
• Avoids state trapping in illegal state
5.
6.
Make Coded State Transition Table
Choose Flip-Flop Type
 For SSI, MSI, LSI JK works best – simplifies
Next State & Output decoders
 For VLSI and ULSI, Use D flip-flops
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Design Lecture 12
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Synthesis (concluded)
Obtain Flip-Flop Excitation Tables
8. Complete & Minimize Flip-Flop Excitation
Equations
9. Complete & Minimize Flip-Flop Output Equations
10. Complete Sequential Circuit Design
7.
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Example
1
0/0
2
0/0
1/0
1/0
3
0/0 0/0
1/0
7
1/0



0/0 0/0
4 1/0
5 1/1
0/0
6
1/1
Produce 1 on z output after 4+ consecutive 1’s
on input x after at least one 0 input on x
Assume that x is synchronized with the clock
State Diagram – Mealy Machine
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Final State Transition Table
State
1
2
3
4
5
6
7
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0
2/0
2/0
2/0
2/0
2/0
2/0
2/0
x
1
7/0
3/0
4/0
5/0
6/1
6/1
7/0
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State Reduction


# Flip-Flops =  log2 (# states)
 States 5 & 6 are equivalent
 States 1 & 7 are equivalent
Reduced State Transition Table
x
1
State
0
1
2/0 1/0
2
2/0 3/0
3
2/0 4/0
4
2/0 5/0
5
2/0 5/1
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Design Lecture 12
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State Assignment

Assign binary codes to state names
State y1
0
1
0
2
0
3
0
4
1
5
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y2
0
0
1
1
1
y3
0
1
1
0
0
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Coded State Transition Table
x
State y1
0
1
0
2
0
3
0
4
1
5
1
1
1
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y2
0
0
1
1
1
1
0
0
y3
0
1
1
0
0
1
1
0
0
001/0
001/0
001/0
001/0
001/0
XXX/X
XXX/X
XXX/X
1
000/0
011/0
010/0
110/0
110/1
XXX/X
XXX/X
XXX/X
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Flip-Flop Selection and Output
Decoder



Select D flip-flops
Flip-Flop Excitation Table
y1x
Output Karnaugh Map
y2y3
 z = x y1
00
01
11
10
7/18/2015
Qt Qt+1
0 0
0 1
1 0
1 1
00 01
0
0
0
0
0
0
0
0
Bushnell: Digital Systems
Design Lecture 12
D
0
1
0
1
11
X
X
X
1
10
X
X
X
0
35
K-Maps for Next State Decoder
y1x
y2y3
00
01
11
10
y1x
y2y3
00
01
11
10
D1
00 01 11
0
0
X
0
0
X
0
0
X
0
1
1
D3
00 01 11
1
0
X
1
1
X
1
0
X
1
0
0
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X
X
X
0
10
X
X
X
1
y1x
y2y3
00
01
11
10



D2
00 01 11
0
0
X
0
1
X
0
1
X
0
1
1
D1 =
D2 =
x (y2
D3 =
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Design Lecture 12
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X
X
X
0
x y2 y3
x y3 + x y2 =
+ y3)
x + y2 y3
36
Final Machine
x
y2
y3
x
y2
y3
x
y2
y3
CLK
7/18/2015
D1 Q1
y1
z
C Q1
y1
D2 Q2
y2
C Q2
y2
D3 Q3
y3
C Q3
y3
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Design Lecture 12
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Problems
1.
2.
No way to initialize machine – comes up in
randomly-chosen state in real hardware
 SOLUTION: Add reset line and initialize all
flip-flops
If machine fails during operation & goes into
undefined state, no guarantee that it will ever
reenter a legal state
 SOLUTION: Design next state decoder so
that a path always exists from undefined
states to legal states
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Design Lecture 12
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Problems (continued)
3.
Sequential Machines cannot be tested
 SOLUTIONS:
1. Choose state assignment to allow testing
2. Add test mode to guarantee initializing
sequence for all states
3. SCAN design – in test mode, all flip-flops
become a giant shift register
• Can shift in and shift out states
4. Partial SCAN Design – Apply Method 3 only
to selected flip-flops
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Design Lecture 12
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Corrected State Machine
Design
1
0/0
2
1/0
3
0/0 0/0
1/0
0/0
4 1/0
5
0/0
1/0
X/X
6
7/18/2015
1/1
X/X X/X
7
8
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Design Lecture 12
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Corrected State Transition
Table
State
1
2
3
4
5
6
7
8
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0
2/0
2/0
2/0
2/0
2/0
1/0
1/0
1/0
x
1
1/0
3/0
4/0
5/0
5/1
1/0
1/0
1/0
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Design Lecture 12
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Improved Coded State
Transition Table
x
State y1
0
1
0
2
0
3
0
4
1
5
1
6
1
7
1
8
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y2
0
0
1
1
1
0
0
1
y3
0
1
1
0
0
0
1
1
0
001/0
001/0
001/0
001/0
001/0
000/0
000/0
000/0
1
000/0
011/0
010/0
110/0
110/1
000/0
000/0
000/0
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Changed Karnaugh Maps
y1x
y2y3
00
01
11
10
y1x
y2y3
00
01
11
10
D1
00 01 11
0
0
0
0
0
0
0
0
0
0
1
1
D3
00 01 11
1
0
0
1
1
0
1
0
0
1
0
0
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0
0
0
0
10
0
0
0
1
y1x
y2y3
00
01
11
10
y1x
y2y3
00
01
11
10
D2
00 01 11
0
0
0
0
1
0
0
1
0
0
1
1
00 01
0
0
0
0
0
0
0
0
Bushnell: Digital Systems
Design Lecture 12
z
11
0
0
0
1
10
0
0
0
0
10
0
0
0
0
43
Changed Equations




D1 = x y2 y3
D2 = x y2 y3 + x y1 y3
D3 = x y1 + y1 y2 y3 + x y2 y3
z = x y1 y2 y3
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Design Lecture 12
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Improved Logic Diagram
x
y2
y3
D1 Q1
z
y1
y3
C Q1
x
y1
y3
x
y1
y2
y3
CLK
x
y2
y3
7/18/2015
D2 Q2
y1
y2
C Q2
y2
D3 Q3
y3
C Q3
reset
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Design Lecture 12
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Implementation Comparisons
Old Implementation
1 3-input AND
3 2-input AND
2 2-input OR
1
Inverter
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New Implementation
1 4-input AND
4 3-input AND
1 2-input AND
1 3-input OR
2 2-input OR
1
Inverter
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Design Lecture 12
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Summary





Hardware design approach
Mealy and Moore Machines
Edge-Triggered Flip-Flops
State Machine Analysis
State Machine Synthesis
7/18/2015
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Design Lecture 12
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