Transcript A 32-Bit Computer for LatticeXP2 Brevia Development Kit

FPGA VHDL eP32 Design
2012 FIG Taiwan Conference
February 17, 2012
Chen-Hanson Ting
Summary
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Brevia FPGA Development Kit
Architecture of eP32
Implementing eP32
Memory and IO
Brevia Board and LatticeXP2
ispLEVEL and Diamond IDE
Demomnstration
Brevia FPGA Development Kit
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Lattice XP2 Brevia Kit is a complete
FPGA development system for $49.
The FPGA chip on Lattice Brevia Kit let
us design and implement your own
microcontrollers.
A 32-bit Forth microcontroller eP32 is
demonstrated here.
Brevia FPGA Development Kit
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For $49, you can design, build and test
your own microcontroller.
The on-board FPGA chip, LatticeXP5E,
can host a complete 32-bit
microcontroller system.
eP32 is implemented in VHDL, with
Forth operating system and
programming language.
LatticeXP2 Brevia Kit
Brevia Board
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LatticeXP2-5E 6TN144C FPGA
2-Mbit SPI flash memory
128K by 8-bit SRAM
8 switches/pushbuttons
8 status LEDs
USB download and serial cable
LatticeXP2-5E 6TN144C
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5K LUT4 Logic cells
166K Bits Embedded block memory
10K Bits Distributed memory
3 DSP Blocks
12 18x18 Multipliers
144 Pin TQFP Package
The Most Satisfying FPGA
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I have tried FPGA’s from all Big 4:
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Market Share
Xilinx
50%
Altera
30%
Lattice 10%
Actel
6%
2009 Sales
$1,825M
$360M
$194M
$190M
FPGA
Virtex, Spartan
Stratix, Cyclone
ECP3, XP2
IGLOO, ProASI
Lattice has the most satisfying FPGA, a single chip
SOC solution
Lattice has the cheapest development board. $49
Lattice provides free development software.
Brevia Design Tools
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ispLEVEL or DIAMOND IDE
Synthesis: Synplify
Simulation: Active-HDL from Aldec
Layout: Design Planner
Flash Programming: ispVMR
Tracing and Debugging: ispReveal
Architecture of eP32
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A 32-bit CPU (Central Processing Unit)
Two stacks to support Forth Language:
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Return stack for nested return addresses
Parameter stack to pass parameters among
nested subroutines
Minimal instruction set
Single clock cycle execution time
Optimized subroutine call and return
Block Diagram of eP32 CPU
ALU and Data Processing Unit
Program and Data Memory Unit
Return Address Processing Unit
Instruction Execution Unit
Instruction Execution Timing
Instruction Set of eP32 CPU
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Minimum Instruction Set Computer
(MISC)
Only 27 Instructions, expandable to
64 instructions
4 Types of instructions:
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Program transfer instructions
Memory access instructions
ALU instructions
Register and stack instructions
Program Transfer Instructions
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BRA
RET
BZ
BC
CALL
NEXT
Branch always
Return from subroutine
Branch on zero
Branch on carry
Call subroutine
Loop until R is 0
Memory Access Instructions
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LDX
LDXP
LDI
STX
STXP
Load from memory
Load from memory and
increment X register
Load immediate value
Store to memory
Store to memory and
increment X register
ALU Instructions
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ADD
AND
XOR
COM
SHR
SHL
RR8
MUL
DIV
Add S to T
AND S to T
XOR S to T
One’s Complement of T
Shift T to right
Shift T to left
Rotate T right by 8 bits
Multiplication step
Division step
Register and Stack Instructions
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DUP
DROP
PUSH
POP
OVER
TX
XT
NOP
Duplicate T to S
Pop S to T
Push T to R
Pop R to T
Duplicate S over T
Load X to T
Store T to X
No operation
Implementing eP32
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eP32_chip.vhd, top level design
eP32q_tb.vhd, test bench
Modules
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eP32.vhd, CPU core
Ram_memory.vhd, 4096x32 autoinitialized RAM memory
Uart.vhd, 115200 baud
Gpio.vhd, 16 bit bidirectional
Synthesizing eP32
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Ep32.vhd, uart.vhd and gpio.vhd are
synthesized without modification
Ram_memory.vhd must be constructed
to use RAM_Q modules in LatticeXP2-5E
FPGA chip.
Ep32_chip.vhd instantiates new
ram_memory.vhd with all other modules
Simulating eP32
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Active-HDL simulation tools are supplied
by Aldec.
ispLEVEL needs a test bench module for
functional simulation of eP32 chip:
ep32q_tb.vhd
DIMOND simulates ep32_chip directly.
Memory and IO
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Design Planner to assign following
signals to physical pins:
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External reset
External master clock
Interrupts
GPIO to LED and switches
UART transmit
UART receiver
Programming XP25E FPGA
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Connect USB cable to PC.
Invoke Programmer to download
ep32_xp2.jed file.
eP32 eForth boots up and sends signon message to HyperTerminal console.
Demonstration
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Boot up eForth on eP32.
Universal greeting “Hello, World!”.
Turn LED’s on and off.
Read switches and push buttons.