Transcript A Primer on CMOS Technology

A Primer on CMOS
Technology
Objectives:
1.To Introduce about CMOS technology
Basic CMOS Fabrication Flow
Fabrication Steps
Lithography
Key Characteristics:
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Bulk Process
Twin Wells
Shallow Trench Isolation
Poly gate material
Lightly doped Source/Drain extensions
Salicided gate,drain source areas
Subtractive metarialzation
The Fabrication Steps
FEOL
BEOL
Front-End-Of-Line :
1.Initial Wafer
• Either p-type or n-type wafer
• Epitaxial layer of gentle doping
2.n-well Formation
• A mask is used to define the geometry of n-well
• Donor atoms are implanted into indicated region
• This will be p-channel MOSFET
3.p-well Formation:
• Do the complementary job of n-well formation
4.Active area definition:
• MOSFETs & diffusion areas are defined by
subsequent mask
• Thin buffer oxide layer SiN layer is used to cover the
entire surface
5.Shallow trench isolation:
• Trenches are cut into the bulk materials
• Trenches filled up with oxide materials
• Remove the materials by using Chemical mechanical
polishing
• CMP is used to get most planer surface which is
essential for photolithography process
6.Gate dielectric Formation:
• The Wafer is layered by extremely thin (2nm-5nm) oxide layer
7.Polysilicon Deposition and patterning:
• The entire surface is covered with poly silicon film(200nm)
8.n-channel source/drain extension:
• N-type material is imposed to extend the source &
drain
9.p-channel source/drain extension
• Do the complementary job of n-channel
10.Side-wall or oxide spacers:
• An oxide layer is deposited and etched away to leave an
insulating wall
11.n-type doping:
• A heavier and deeper implant is used to make drain
and sources of the n- channel MOSFETs
• Side wall spacers prevent penetration of doping atoms
12.p-type doping:
• Complementary job of n-type doping is done here
13.Salicidatioin :
• Wafer is covered by thin Highly conductive silicide film
• That serve lower electrical resistivity to source drain and
gate
Back-End-Of-Line:
1.First interlevel dielectric :
o Layer of Silicon dioxide is deposited
o Another CMP planarization step is done to make layer
the first interevel dielectric
2.Contact plug formation:
o Mask CONTACT defines the region where metal shell
connect to adiffusion or polysilicon region
o Tungsten is deposited to form the plug
3.Deposition of patterning of first metal layer:
o Metal layer is deposited entire the layer
surface
o Metal layer removed selectively to leave
behind those parts that are defined metal1
mask
4.Second inter level dielectric:
o The second interlevel dielectric deposited and
planarized
5.Via plug formation:
o Mask via1 defines those location where a first metal
structure shall connect
6.Deposition of patterning of second metal layer:
o The Second layer of metal is obtained by way of
subtractive metalization
7.Third interlevel dielectric followed by via plug
formation:
o Dielectric deposition , planarization , plug
formation , metal deposition and metal
patterning is done in this step
o Two mask is required per metal layer
8.Deposition of patterning of third metal layer :
o Topmost metal layer
9.Overglass and bond pad openings :
o The Wafer surface is covered by a Layer of Silica
Process Monitoring:
• Capcitance-Voltage Characteristics are obtained from MOSCAP
• The Resistivity of all Conductive layer is determined Van der Pauw
structure .
• Fault Wafers are detected and sorted out
Photolithography
Photolithography has Four major Parts:
1.An Illumination Source
2.A mask
3.An exposer subsystem
4.Photoresist Materials
A Practical Photolithographic machine:
Traditional optical Lithography:
o 546 nm E-line
o 436 nm G-line
o 405 nm H-line
o 364 nm I-line
Deep UV Lithography:
o 248 nm (KrF6)
o 193 nm (ArF6)
o 157 nm (F2)
Resolution Enhancement Techniques:
1.Phase Shift Masks:
o Improving line Separation by cancelling out light
waves using destructive interference
o Illumination must be from a partially coherent
source.
2.Off-axis Illumination:
o
Like as Phase shift masking
o
But there is no extra phase shifter
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Slightly tilted illumination axis
3.Optical Proximity Correction:
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Applies inverse distortion to the mask to precompensate
the inperfection
o
Overaccutuated corners such as serifs and hammer heads
are typical for OPC
4.Computerized resolution enhancement :
PSM & OPC are used in computerized way in high
volume high repetitive layout ( like RAM)
Post Optical Lithography:
1.Electron beam direct write lithography:
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Layout pattern get written in photoresist layer by an electron beam
o
It is too slow for mass production
2.Nano imprint lithography:
o Here Photoresist is not used
o Patterns are printed on polymer coating by
pressing a stencil on the wafer surface
Some Change Has been made in Fabrication
Industry:
o Copper Has Replaced Aluminum as interconnect
material:
First Fabrication process with Cu as
Interconnect material :
o Low-permittivity interlevel dielectrics are replacing Silicondi-oxide:
Low permittivity dielectric is using for
1.Good mechanical strength
2.Process Compatibility
3.Thermal Stability
4.Low moisture absorption
Intel’s 65 nm processed material where Carbon
doped oxide CDO (€r=2.9)is used as interlevel
dielectric instead of Silicon-di-Oxide(€r=3.9)
THE END