Transcript Digital Counters 1

Counters
Basic terminology associated
with counters
Technician Series
©Paul Godin Counters
Updated Jan 2015
1
Introduction
Counters are part of a family called Sequential Circuits.
Sequential circuits provide predictable output patterns.
Sequential circuits are used in many applications,
including:
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digital counting
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•
counting up or down
arithmetic operations
control circuits
frequency dividers
clocks
timing circuits...
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Introduction
•
Basically, counters are devices that are able to
count clock pulses.
•
Counters are constructed from Flip-Flops
•
Available as counter ICs
Sn74LS192
Up/Down 4-bit counter
with preset and clear
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Digit Significance
• Most Significant Bit (MSB): This bit occupies the position
with the greatest numerical value in a binary number,
and is the left-most bit in a binary number.
• Least Significant Bit (LSB): This bit occupies the position
with the smallest numerical value in a binary number,
and is the right-most bit in a binary number.
• When looking at counter outputs it is important to
remember which is the MSB and which is the LSB.
10110
• Example:
MSB
LSB
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Modulus
•
The Modulus of a counter refers to the number of
unique output states it can produce. Also
referred to as “MOD”.
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Example:
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a counter counts in the following sequence: 000,
001, 010, 011, then back to 000
•
The modulus of this counter is 4. It has 4 unique
output states (including zero).
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Maximum Modulus
•
The maximum modulus of a counter is 2N, where ‘2’
indicates the number of possible bit states (1 or 0),
and ‘N’ represents the maximum number of bits.
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The maximum modulus of a 3-bit counter is 8.
There are 8 unique output states (from 000 to
111).
What is the maximum modulus of a 5 bit counter?
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Counter Sequences
•
A Bit is a single binary digit (1 or 0). A binary
number is comprised of multiple bits.
•
Full Sequence Count refers to a natural count that
includes all possible binary numbers. It’s modulus
is the same as its maximum modulus.
•
A Truncated Sequence Count is when the modulus
is less than its maximum, or where less than all
possible binary numbers are used.
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Sequential Circuit
•
•
Counter states are sequential. An output state will
follow another in a sequence.
State Diagrams are used to visually represent the
sequence of these states.
000
100
001
011
010
State Diagram of a truncated sequence
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Sequential Circuits
Counters normally recycle or restart their sequence.
Example:
000
111
001
110
010
101
011
100
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Up/Down
A natural count can be Up or Down:
000
111
001
000
UP
110
010
111
001
011
101
DOWN
010
100
011
110
101
100
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State Table
•
•
A State Table is another means of presenting state
sequences.
As with the state diagram, the state table determines
the next output based on the present output state.
Current
QC QB
Next
QA
QC
QB
QA
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
0
0
0
Returns to the
first state.
State Table
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Review Questions
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A truncated mod-6 3-bit up counter has a starting
point of all low outputs.
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Draw the state diagram
Draw the state table
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If a full sequence down counter has a current
output of 0101, what is the next output?
•
If a counter requires a modulus of 130, what is the
minimum number of bits required?
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Asynchronous Counters
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Binary Counting
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
If one looks at the changes
in individual bits of a binary
count from one value to the
next, a frequency pattern
emerges.
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
↓ ↓ ↓
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Binary Counting
f
0 0 0
0 0 1
0
1
0
1
0
1
0
1
½f
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
↓ ↓ ↓
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
¼f
Each more significant digit has half the
frequency of the previous digit.
A divide-by-two frequency divider can be
used to build a counter.
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Frequency Division
A device that divides the input frequency by 2 is a
toggling JK flip-Flop
1
J
Q
Clk
1
K
Q
T
T
Clk
Q
T
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Asynchronous Counter
To count in binary, the frequency of each more
significant bit needs to divide the previous bit’s
frequency by 2.
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4-bit Binary Counter
Note the labeling standard for counters.
The LSB is always “A”
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Asynchronous
• The counter bits are not clocked in synchronization;
the source is applied to the first flip-flop only. This
counter design is therefore asynchronous (not
synchronous).
• It takes time for the clock edge to work its way
through each flip-flop. Propagation delay is the cause
of this effect.
• Because of the output pattern where the edge works
its way through each flip-flop, asynchronous counters
are also known as Ripple Counters.
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Timing Diagrams
• It is important to remember to look at the state of
the inputs just before the edge when drawing timing
diagrams.
• When looking at the timing diagram, remember to
identify the MSB and the LSB. The LSB is the FlipFlop closest to the external clock input.
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Reading a Counter Timing Diagram
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
LSB
MSB
Based on the observed pattern, the least significant bit
(LSB) is represented at the top of the timing diagram and
the MBB is at the bottom.
The values must be read from the bottom up (MSB to LSB).
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Truncating
• Truncating is when a counter is prevented from
reaching its maximum modulus.
• For example, a 3-bit mod-5 counter will have 5
unique states but will not have the maximum
modulus of 23, or mod-8.
000
Values 101, 110 and 111 are
not included in this sequence
100
001
011
010
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Truncating Method
•
The most common method of truncating a count is
to:
1. Detect the presence of the first unwanted value using
logic gates
2. Immediately reset or preset the counter back to the
desired starting state
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Truncating Method
Next
natural
state
101
000
100
The time from detection to
an immediate reset is the
time it takes for a signal to
travel through the logic
gates (nanoseconds).
001
011
010
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Truncating Circuit
Detect 101
Counter
Reset
all
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Truncating circuit in EWB
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Frequency Division
•
A typical application for asynchronous counters is
frequency division.
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Example: Use a 60 Hz source to supply 1 pulse per
second (1 pps)
60Hz
Mod-6
10Hz
Mod-10
1Hz
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Frequency Division
Mod-6
60Hz
QC
Mod-10
1Hz
QD
1001
101
0000
1000
000
0001
DCBA
100
001
011
010
CBA
000
001
010
011
100
101
Note the MSB has
a frequency of
1/6th the input
frequency (at 33%
Duty Cycle)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
0111
0010
0011
0110
0101
0100
Note the MSB has
a frequency of
1/10th the input
frequency (at 20%
Duty Cycle)
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Count Direction
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To reverse the count direction of an asynchronous
counter, the following 3 circuit changes can be
applied:
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Change the clocking edge with a different Flip-Flop
Change Q to Q’ in the design
Complement the output (use the Q/Q’ output)
Note that making two changes (reversing the
direction twice) will revert back to the original
direction.
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©prgodin @ gmail.com
Updated Jan 2015
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