Transcript Folie 1 - uniud.it

AMO/AMICA
ULIS 2003
Nanoscale SOI-MOSFETs with Non-Planar
Multiple Gates
M. Lemme, T. Mollenhauer, W. Henschel, T. Wahlbrink, H. Kurz
Advanced Microelectronic Center Aachen (AMICA), Aachen,
Germany
M. Baus, B. Spangenberg
Institut für Halbleitertechnik, RWTH-Aachen, Germany
4th European Workshop on
Ultimate Integration of Silicon
March 20-21, 2003
17.07.2015
AMO/AMICA
ULIS 2003
Nanoscale SOI-MOSFETs with Non-Planar Multiple Gates
Outline
• Device Design and Fabrication
• Influence of Device Geometry
• Influence of Back Gate Bias
• Conclusion
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ULIS 2003
Planar SOI-MOSFET
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Top-Silicon thickness:
BOX thickness:
Gate Oxide:
Channel doping:
S/D/G-doping:
tSi=100nm
tBOX=200nm
tox=8nm
Nch=3e17/cm³
Nd=1e20/cm³
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ULIS 2003
Triple-Gate SOI-MOSFET
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Top-Silicon thickness:
BOX thickness:
Gate Oxide:
Channel doping:
S/D/G-doping:
tSi=100nm
tBOX=200nm
tox=8nm
Nch=3e17/cm³
Nd=1e20/cm³
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ULIS 2003
Gate-Length and MESA-Width Variations
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Top-Silicon thickness:
BOX thickness:
Gate Oxide:
Channel doping:
S/D/G-doping:
tSi=100nm
tBOX=200nm
tox=8nm
Nch=3e17/cm³
Nd=1e20/cm³
Planar MOSFET
Gate-Length MESA-Width
Lg [nm]
WM [nm]
1000
1450
180
82
90
62
70
42
22
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Triple-Gate MOSFET
(FinFET)
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ULIS 2003
Fabrication Process
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• Boron Ion-Implantation
• E-Beam Lithography (HSQ)
Photolithography
• Anneal
1h •6@:O1000°C
HSQ
E-Beam Marker
Etch (SF
2) as Hard-Mask for
• Channel
Doping:
• RIE 3e17/cm³
MESA Etch (HBr, two step process)
Through Top-Si
and BOX
• Profile and Selectivity to BOX
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ULIS 2003
Fabrication Process
WM=42nm MESA
Cross sectional SEM
Channel
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PolyGate
GateModified
RCA-Clean
Thermal
Oxidation @ 900°C (tox=8nm)
Oxide
Poly-Deposition by LPCVD tBOX
Poly=150nm
E-Beam Lithography (HSQ)
• Selective Removal of HSQ
HSQ as Hard-Mask for • Self-Aligned Arsenic Ion Implantation
RIE Gate Etch (HBr, two• step
RTAprocess)
(20 sec @ 1000°C )
Profile and Selectivity (50:1) to Gate-Oxide
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ULIS 2003
Fabrication Process
Exploratory Device Design
• Long S/D-Areas to account for
Proximity Effects
• 8nm Gate-Oxide to avoid GateLeakage-Currents
• „Low“ S/D/G doping to reduce
scattering under Gate
• Simulation (Silvaco ATHENA):
50nm diffusion under Gate
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© AMO GmbH 2003
AMO/AMICA
ULIS 2003
Nanoscale SOI-MOSFETs with Non-Planar Multiple Gates
Outline
• Device Design and Fabrication
• Influence of Device Geometry
• Influence of Back Gate Bias
• Conclusion
Lg
Gate
MESA
BOX
Bulk-Si
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Side-Gate
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Planar MOSFET: Lg Variation
Transfer Characteritics
MESA-Width: WM=1450nm
Short Channel Effects:
DIBL
Punch Through
Subthreshold Swing Degradation
GIDL
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Planar MOSFET: Lg Variation
• Gate-Length: Lg1= 1µm
– No DIBL (<2mV)
– Sub-Vth-Swing:
• S0,1V= 73mV/dec
• S1V= 76mV/dec
• Gate-Length: Lg2= 180nm
– DIBL: 570mV
– Sub-Vth-Swing:
• S0,1V= 144mV/dec
• S1V= 240mV/dec
• Gate-Length: Lg3= 90nm
– DIBL: N/A
– Subthreshold Swing: N/A
– Punch Through !
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Triple-Gate MOSFET: Lg Variation
Transfer Characteritics
MESA-Width: WM=22nm
Short Channel Effects:
Reduced DIBL
Subthreshold Swing Degradation
No Punch Through
Enhanced GIDL
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ULIS 2003
Triple-Gate MOSFET: Lg Variation
MESA-Width: WM=22nm
• Gate-Length: Lg1= 1µm
– No DIBL (<2mV)
– Sub-Vth-Swing:
• S0,1V= 74mV/dec
• S1V= 85mV/dec
• Gate-Length: Lg2= 180nm
– DIBL: 44mV
– Sub-Vth-Swing:
• S0,1V= 70mV/dec
• S1V= 86mV/dec
• Gate-Length: Lg3= 90nm
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– DIBL: 233mV
– Subthreshold Swing:
• S0,1V= 104mV/dec
• S1V= 124mV/dec
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Triple-Gate MOSFET : WM-Variation
Reduction of SCE
Sub-Vth-Swing
Gate-Length: Lg=180nm
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ULIS 2003
Triple-Gate MOSFET : WM-Variation
Reduction of SCE
DIBL
Gate-Length: Lg=180nm
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ULIS 2003
Triple-Gate MOSFET : Conclusion
Gate-Length: Lg=180nm
Triple-Gate Control
strongly reduces
Short Channel Effects
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ULIS 2003
70nm Multi-Gate MOSFET
Output
Characteristics
Low Ion
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Transfer
Characteristic
Negative Vth
Work-Function engineering necessary for CMOS-integration
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ULIS 2003
70nm Multi-Gate MOSFET
Subthreshold Swing
Lg=70nm
Sub-Vth behavior strongly dependent on MESA-Width
S0,1V= 120mV/dec S1V= 203mV/dec
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ULIS 2003
Triple-Gate MOSFET : On-Current
On-Current decreases for
constant Gate-Overdrive
Drastic decrease for 22nm
devices
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Triple-Gate MOSFET : Current-Density
Current density increases for
constant Gate-Overdrive
down to WM=42nm
• Inversion Channel ~ 10nm
• Current primarily on surface
• Surface:Volume ratio increases
for narrow MESAs
• Current density increase
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ULIS 2003
Triple-Gate MOSFET : Current-Density
Current density decreases
drastically for Lg=22nm
devices
Current limited by large
parasitic S/D resistance due
to edge roughness and
surface charges (mobility
degradation)
Metallic S/D needed to
overcome this problem
17.07.2015
© AMO GmbH 2003
AMO/AMICA
ULIS 2003
Nanoscale SOI-MOSFETs with Non-Planar Multiple Gates
Outline
• Device Design and Fabrication
• Influence of Device Geometry
• Influence of Back Gate Bias
• Conclusion
17.07.2015
© AMO GmbH 2003
AMO/AMICA
ULIS 2003
Planar MOSFET: Back Gate Influence
Gate Length : Lg=180nm
MESA Width: WM=1450nm
Cross Section
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ULIS 2003
Planar MOSFET: Back Gate Influence
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Forming of back-gate inversion
channel degrades Sub-VthSwing (Vbgs>0V)
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Enhanced Sub-Vth-Swing for
negative Vbgs / back-interface
accumulation
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ULIS 2003
Triple-Gate MOSFET: Back Gate Influence
Gate Length : Lg=180nm
MESA Width: WM=22nm
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No back-gate inversion channel
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No influence of Back Gate on
Subthreshold Swing
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Modification of Vth
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ULIS 2003
Back Gate Influence
Subthreshold Swing
Threshold Voltage
Gate-Length: Lg=180nm
Gate-Length: Lg=180nm
Suppression of back-gate influence in narrow channel devices
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ULIS 2003
Conclusion
• Reduction of Short Channel Effects due to the
implementation of Multiple-Gates
• Demonstration of Lg=70nm Triple-Gate n-MOSFET
(FinFET-like structure)
• Current limitation due to parasitic S/D-resistance in
Nano-scale devices
• Suppression of Back-Gate influence in narrow
channel devices
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ULIS 2003
Thank you for your attention!
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AMO/AMICA
ULIS 2003 - Backup
Back-Gate MOSFET: WM=1450nm
Output
Characteristics
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Back Gate Characteristics
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Lg=180nm
Transfer
Characteristics
AMO/AMICA
ULIS 2003 - Backup
Back-Gate MOSFET: WM=22nm
Output
Characteristics
17.07.2015
Back Gate Characteristics
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Lg=180nm
Transfer
Characteristics