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DH2T 34 – HNC Computer
Architecture 1
Lecture 14
The Fetch-Decode-Execute Cycle [1].
© C Nyssen/Aberdeen College 2003
All images © C Nyssen/Aberdeen College except where stated
Prepared 8/12/03
We saw last time that low-level programs are run in
Assembly Language. No matter what type of processor is
used, each assembly code instruction usually comes in two
parts – an OPCODE and an OPERAND.
To start, look at the instruction
set for the processor, to get an
idea of what the program does,
before doing an assembly code
trace.
All the examples shown here
will use the “beginners” set in
the pink workbook.
#assembly code program
0000 LDA-24
0001 ADD-25
0002 HLT
#loads
#adds
#stops
#end of program
Opcodes are sometimes called “mnemonics” because they do
what they sound like!
To begin, all the instructions are loaded into the RAM.
In a CISC processor, the instructions will be different
sizes. In a RISC, they will all be 32-bits wide.
For the
moment,
however,
we will
assume
that they
are all the
same size.
The CPU now fetches each instruction in turn, decodes
and executes it. This is called the FETCH-DECODEEXECUTE cycle.
The FDE Cycle has 3 distinct phases –
FETCH - the CPU collects the instruction from RAM
DECODE - the Control Unit figures out what to do with it
EXECUTE - the instruction is carried out.
The FETCH and DECODE phases never vary. The
EXECUTE phase may be different each time, because it
depends on what the instruction was!
For this example we will assume a “cold boot” to start –
i.e. all the internal registers are set at zero.
FETCH
First the
Program
Counter
copies its’
contents to
the MAR.
Whenever a new value enters the MAR, this is the signal
for it to point to the matching RAM address using the
Address Bus.
So in this case we are pointing at location 0000.
When the pointer hits the RAM cell, this is a trigger for it to
dump its’ contents on the Data Bus and send them back to
the MDR.
The MDR will now contain the value LDA-24.
The contents of the MDR now get transferred to the
Instruction Register, ready to be decoded.
This is the end of the FETCH part of the instruction.
DECODE
The Decoder in the Control
Unit takes the instruction and
splits it into the two parts –
the opcode and the
operand.
opcode
operand
In this example the opcode LDA tells us to load
the accumulator with data.
The Operand 24 tells us where the data will
come from.
At this point the PC also increments itself by 1.
EXECUTE
This will vary
between
instructions.
In this case we
are loading the
accumulator
with a value
taken from a
RAM location.
To bring the data back, we first have to set up the MAR
again so it is pointing at the correct cell. The 24 is put in
the MAR, triggering it to point to RAM address 24.
When the pointer hits address 24, this is the signal for it to
dump the contents onto the Data Bus. So the value 6 is
sent back to the MDR.
The whole instruction was to load the accumulator with
the value, so we copy in the 6.
This is the whole instruction completed and we are now
ready to begin the next one.
Note that
the values in
the registers
do not
change until
a new value
arrives to
overwrite
them.
FETCH
The PC copies its’ contents to the MAR. This signals it to
point to RAM location 0001.
The
contents of
0001
(ADD-25)
are dumped
on the Data
Bus and
brought
back to the
MDR.
The ADD-25 is copied to the Instruction Register,
where the decoder splits it into ADD and 25.
Remember to increment the Program Counter!
EXECUTE
In this case we are ADDing whatever is in RAM address
25, to the value already in the Accumulator. Because we
have to retrieve the contents of 25 first, we have to set up
the MAR again.
The address bus points to the correct RAM address, which
dumps the contents on the Data Bus and returns them to
the MDR.
This value is then passed to the Accumulator and added
on to what is already there.
FETCH
The PC copies its’ contents to the MAR, which is
triggered to point to RAM location 0002.
The contents of 0002 are brought back along the Data Bus
and transferred to the MDR.
DECODE
The MDR contents are taken to the IR to be decoded.
The PC increments by 1.
EXECUTE
In this case there is no operand, just the Opcode, so the
MAR does not change.
The instruction HLT means “stop the program” so
nothing else will happen from here on.
The space that the program occupied in RAM will be
overwritten by the next program to be loaded and run.
In some books the Fetch-Decode phases are shown as
just a Fetch phase, and the cycle is just called the FetchExecute Cycle.
The point at which the PC increments can also vary
depending on processor models.
For your first assessment
question you will be required to
trace several instructions through
the processor, showing the
different values in the registers at
each stage.
Summary [1]
 To run the program, first the instructions are
loaded into RAM.
 The CPU then fetches, decodes and
executes each instruction in turn.
 The Fetch and Decode phases are always
the same but the Execute phase will vary.
Summary [2]
FETCH –
 PC -> MAR. MAR points to correct RAM address.
 Contents of address are brought back to MDR.
 Contents are passed to the IR for decoding.
DECODE
 Instruction is split into an Opcode and Operand.
 PC is incremented by 1.
EXECUTE
 This may involve setting up the MAR again, loading
or moving values, or performing arithmetic or logic
operations.