Transcript No Slide Title

Operating systems and processors
and storage
Revision
Storage media
Microprocessors
Operating systems
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The data on a disk is stored in a binary form as
magnetic dots along the tracks.
The read/write head (R/W head) detects the polarity,
because there are only two polarities, there are only
two states.
The pattern of pulses produced by the R/W head in
relation to the drive timing is translated into data and
sent to the CPU.
Optical media
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Disk has holes burnt in it by a laser to record the binary
code.
A hole or pit on the disk reflects less light than the
surface of the disk.
By detecting the difference in reflected light in relation
to the time of the drive, a pattern of pulse is produced
and this is translated into data sent to the CPU.
Compact Disks and DVD
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CDs –
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optical media storing approximately 650MB of data.
Use basic principle on previous slide.
DVD
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the same basic principle as a CD,
data is packed more densely it has a larger capacity (4.7GB)
as compared to a CDs 650MB, smaller and narrower pits.
quicker transfer rate than a CD.
Better compression algorithms help to improve the capacity.
Microprocessors
Fetch
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All programs are stored in memory, and have to be
‘fetched’ from memory before they can be carried out
(executed).
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Before the CPU can use an instruction, the instruction
must be brought to the CPU from the memory.
Starting with a program counter (PC) this points to
the memory location/address of the next
instruction to be executed.
Therefore, if the contents of the PC were 5, the next
instruction to be executed is stored in memory
location 5.
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The contents of the program counter are copied to the
memory address register (MAR).
The program counter contents are then incremented
to the next instruction.
The MAR holds the address of the memory
location where in memory the data is to be used is
located.
Note: The MAR does not just do this in the fetch part. If you
taking something out of memory or putting something into
memory the address of the memory location has to be there
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The contents of MAR during this part of the cycle
contains address of the instruction to be executed, the
contents of this memory location are placed into the
memory data register (MDR).
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During this part of the cycle the data that is passed
from memory is an instruction.
The instruction is moved from the MDR to the
instruction register (IR) where it is divided into two
fields.
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One field is the operation code often shortened to
opcode, which tells the CPU the instruction to carry
out.
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The second field is the operand field, which contains
the address/data (or addresses) of data used by the
instruction. Sometimes the operand field is not used.
RTL (Register Transfer Language) for
fetch part of the cycle.
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Short hand notation for describing register
transfers
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[MAR][PC]
[PC][PC]+1
[MDR][M([MAR])]
[IR][MDR]
CU[IR(opcode)]
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The next stage is the decode-execute cycle where
the control unit takes the opcode from the
instruction register, and generates the control
signals to control the various parts of the CPU.
The control unit is responsible during the fetch
cycle for all the operations to make the fetch
happen
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Pipelining is a key technique used to make
faster CPUs.
Processors allow instructions to be executed in
stages; stages implemented using separate
hardware.
Stages connected together forming an
instruction pipeline, allowing more than one
instruction to be processed at the same time.
Fetch-execute
cycle
stages
fetch
1
decode
execute
instruction 1
2
instruction 1
3
instruction 1
4
5
6
7
8
write-back
instruction 1
instruction 2
instruction 2
instruction 2
instruction 2
Pipelining
cycle
1
2
3
4
5
6
7
8
stages
fetch
instruction
instruction
instruction
instruction
instruction
instruction
instruction
instruction
decode
1
2
3
4
5
6
7
8
instruction
instruction
instruction
instruction
instruction
instruction
instruction
execute
1
2
3
4
5
6
7
instruction
instruction
instruction
instruction
instruction
instruction
write-back
1
2
3
4
5
6
instruction
instruction
instruction
instruction
instruction
1
2
3
4
5
Speed up
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If a k-stage pipeline executes
n instructions using a clock
with a cycle time t, without
overlapping instructions the
total time to execute
instructions will be
So if 4 stages are used (k=4),
4 instructions (n=4), and
t=1s, Ts=16s.
Ts  nkt
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If instructions are executed in
parallel, where kt is the time
to fill-up to the point where
the first instruction completes
and (n-1)t is time taken for
the remaining (n-1)
instructions at a rate of one
per clock cycle.
Tp  kt  (n 1)t
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Speedup factor,
S=Ts/Tp=(nk)/(k+n-1)
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If n=50 (50 instructions in a sequence)
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S= (50*4)/(4+50-1)=3.77
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If n=100 S=3.88
ADDRESS
REGISTER
10
11
12
13
14
15
16
17
18
19
PC
DATA
CU
SP
ADDRESS
MAR
READ/WRITE
IR
ALU
A
I/O
MEMORY
PSW
MICROPROCESS
OR
CLOCK
K
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Arithmetic and Logic Unit (ALU)
This carries out
arithmetic operations such as adding or subtracting,
and logical operations.
Control Unit (CU) This controls the execution of
instructions.
Input and Output Ports (I/O)
Communicates with the
outside world, either reading in data or sending data
out.
Clock
This produces regular pulses which controls
the rate at which instructions are carried out.
Registers
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A register is a small storage unit which holds a
single piece of data.
Program status word:This register contains
information about the result of operations such
as if the result is negative or zero.
Complex instructions
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Early computers had small, simple instructions.
Computers that are more powerful were wanted, so
more powerful and complicated instructions were
needed.
Complex instructions often lead to faster program
execution, but the time taken to perform an instruction
may take longer.
Complex instructions were also better because the
execution of individual operations could be overlapped,
or otherwise executed in parallel.
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Initially these processors were designed with a
smaller number of instructions around 50, so
name Reduced Instruction set computer
(RISC) in contrast with Complex instruction set
Computer (CISC) (VAX, etc). Later RISC
processors may have larger set of instructions.
Why has RISC not replaced CISC
completely?
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Backward compatibility, billons pounds (or dollars)
have been invested in software for the Intel line
Intel employed some of the RISC ideas in the 486s
upwards. It contained a RISC core to execute simplest
and most common instructions, while the more
complicated instructions in the usual CISC way. So
common instructions are generally fast and less
common instructions are slow.
hybrid approach not a pure RISC design. This allows
higher performance but still allowing old software to run
unmodified.
ALU
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Arithmetic Logic Unit
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Carries out all arithmetic operations
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Carries out all logic operations, including
comparison (>,<.equal to, not equal to, etc) not
just ANDs, Ors, etc.
General principles
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All instructions are directly executed by
hardware
Maximise rate at which instructions are issued
Instructions should be easy to decode
Only load and stores should reference memory
Plenty of registers
All instructions are directly executed by
hardware
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All common instructions are directly executed
by the hardware, eliminating the interpretation
provides higher speed for instructions. CISC
(Complex Instruction Sets) instruction sets,
complex instructions are broken down into
simpler instructions, extra steps slow down, if
these instructions are not frequently used it
may be acceptable
Maximise rate at which instructions are
issued:
Parallelism is a powerful way to improve
performance by using multiple instructions
executed at once.
Instructions should be easy to decode
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A limit on the rate of instructions decode is
determine by what resources are needed.
Making instructions regular, fixed length, and
having small number of fields, are methods
that can aid this process.
Only load and stores should reference
memory:
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Using main memory is slower than registers.
Operations of moving memory to register can
be performed in separate instructions. Only the
load and store instructions should reference
memory.
Plenty of registers
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Accessing memory is slow, so many registers
(over 32) may be needed, and so once data is
fetched, it can be kept in a register until it is no
longer needed. Running out of registers, and
having to send data into memory, only to
reload them is undesirable and should be
avoided as much as possible. An adequate
number of registers are needed.
Example AVR instructions
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ldi
ldi
ldi
r18, 0xff
r18, 0b11111111
r18, 255
These all do the same thing they put the value
(load) of 255 into register r18, as either a
hexadecimal, binary, or decimal number.
Look up some of these other instructions you used
in the practical.
Operating systems
What is an operating system?
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A short definition of an operating system: An
operating system is a collection of system
programs that manage the resources of a
computer and control the running of user
programs.
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Kernel
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Central part of the operating system.
All hardware requests go through the kernel as
system calls
Shell
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The interfaces for the applications programs and
users, with the operating system.
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Process manager deals with
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hardware/software interrupts.
Processor errors
Scheduling tasks
Communication between tasks
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Memory Management
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Allocate memory
Ensures processes (see next week’s lecture) stay
memory boundaries
Controlling virtual memory
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I/0 System
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Communicates with peripherals and hardware
components
Co-ordinates i/o systems such as interrupts and
direct memory access
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Files system
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Organises and accesses files
Maintains on a multi-user system user file quotas
Controls file/record access
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Application Program Interface
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Provides systems services for applications
An interface between the applications and the
operating system.
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User interface
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Allows the user access to programs
Allows the user to view and change system settings.
A consistent interface between the user and the
operating system.
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Most modern operating systems have the ability to
execute several programs at once, although there is
usually only one processor in the system. This is
multiprogramming and is made possible by rapidly
switching the processor between programs. Interrupting
the processor periodically, gives the programs control of
the processor for a short period.
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This switching is triggered by a piece of hardware
called the interval timer, which generates an
interrupt (a time-out interrupt) when the
programmed period has elapsed. The interrupt
handler, then saves the context of the processor.
The context is the contents of registers that may be
overwritten by other programs. Control is passed
over to the dispatcher/low-level scheduler.
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The dispatcher searches a set of potentially
'runnable' program using a scheduling algorithm to
select a suitable program to run next. The context
of the processor, which existed when that program
last ran, is restored to the registers.
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A process consists of an executable program,
the data associated with the program, and it’s
execution context. The execution context
includes the processor context, but also
information such as the process identifier,
priority level, and a process state
Process-3 states
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When a user process is in the running state,
the processor is executing the program code. If
a timer interrupt occurs, the running process is
moved into ready state, and another process
form the list of processes in the ready state is
moved into the running state.
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If a process in the running state requests an
operating system service and it must wait for it,
then the process is moved into the blocked
state.
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A process will remain in the blocked state until
the event required has taken place, the
process can then be moved back into the
ready state. If a process is blocked the
operating system is free to reschedule another
processor.
Virtual Memory 1
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If a system does not have enough physical space to
store data/program it can create space on the hard disk
to acts as memory.
Treated as a file on the disk – swap file.
Slow memory, but better than nothing.
This virtual memory
Less physical memory, more virtual memory is used,
reducing performance.