Predictably Low-Leakage ASIC Design using Leakage-immune Standard Cells

Nikhil Jayakumar Sunil P. Khatri University of Colorado at Boulder

Introduction

    Process feature sizes / operating voltages are diminishing relentlessly. Threshold voltages of the MOS devices reduced along with operating voltages to satisfy speed requirements.

Leakage (sub-threshold) currents increase as a consequence Low leakage crucial for portable electronics to ensure long battery life.

Introduction…2

 Saturation Current Equation: I ds = K(W/L)(V gs –V T ) 2 (1+  Vds) ………….(1)  Sub-threshold Current Equation: I ds = (W/L)I 0 e (Vgs-V T -V off /  v T ) (1-e (-V ds /V T ) )….(2)   From equation(1): need to reduce threshold voltage V T with supply voltage to maintain I ds From equation(2): decreasing V T leakage current exponentially.

increases

  

Previous Work

DTMOS: Dynamic Threshold MOS. Device gate connected to bulk (Assaderaghi et. al.) Results in high-speed switching and low-leakage through body effect control. • •  Drawback: Applicable only when VDD lower than the diode turn-on voltage. • Increased gate capacitance slows the device down.

Proposed for partially depleted SOI designs. Not easily modified to work for other processes

Previous work…2

   VTCMOS: al.) Variable threshold CMOS (Kuroda et. Device V T controlled by dynamically modifying the device bulk voltage Drawbacks:  Need complex circuitry to generate and control the bulk voltages.   Cannot be applied to fully depleted SOI, hard to apply to partially depleted SOI. With future processes the body effect co efficient (  ) will reduce

Previous work…3

   SCCMOS: Super Cut-Off CMOS (Kawaguchi et. al.) Gate of PMOS device (which gates the VDD supply) overdriven during standby reduces leakage dramatically. operation Drawback:  Complex circuitry required to generate the special voltages.

Previous Work…4

 MTCMOS:     Multi-threshold CMOS. (Kao et.al.) ”Power switches” (high V T MOS devices) added between the supplies and the power pins of the circuit. Delay increased (controlled by sizing power switches appropriately). Sizes of power switches for individual logic cells is large.

Device sizing algorithm (based on mutually exclusive discharging of gates) can be used for groups of cells to reduce the size of power switches.

Drawbacks:    Device sizing algorithm works well for regular logic.

Leakage current unpredictable since internal nodes float during standby operation Memory elements need separate supplies.

Our Approach

   Ensure that supply voltage V T .

applied across more than one device and at least one of them is high Ensure that output of each cell is either logic-0 or logic-1 in standby .   Allows precise estimation of circuit leakage.

If input vector to gate (in standby ) is known:  No floating internal nodes. We know which stack (pull-up / pull-down) is leaking.

 Only one power switch required. device (PMOS or NMOS)

Our Approach…2

   So we need two variants of each gate – the “H” and “L” versions “H” cell: Inputs (in output is logic-1 standby mode) such that  Leakage is in pull-down stack  Minimize leakage by gating GND supply with high V T NMOS device “L” cell: is logic-0 Inputs (in standby mode) such that output  Leakage is in pull-up stack  Minimize leakage by gating the VDD supply with a high V T PMOS device

Example – NAND3

NAND3 (H, L variants)

Layout Floor plan

standby standby

Regular Cell L variant H variant   Routing standby abutment).

signals done automatically (by H,L use unmodified cell core from regular cell  Minimizes re-design effort

Sample layout (NAND3-L)

VDD rail

standby

GND rail

standby

Process parameters and sizing

    Used bsim100 predictive 0.1um model cards for our experiments SPICE and MAGIC used for cell design and layout For MTCMOS and H/L gates, the supply gating transistors sized such that delay penalty less than 15% (over the unmodified cell) Up-sizing transistors inside cell core can result in smaller delay and area penalties.  We did not modify cell core

Design Methodology

     Design flow using H/L cells very similar to traditional standard cell based flow:   Optimize and map to standard cell library (SIS).

Given primary input assignment in standby mode:    Simulate circuit, find output value of each gate.

Replace with H / L variant of the gate. Decision made in time linear in size of circuit.

Regular cells from UCBerkeley.

Gates used:  INVA, INVB, NAND2A, NAND2B, NAND3, NOR2, NOR3, NOR4, AND2, AND3, AND4, OR2, OR3, OR4, AOI21, AOI22, OAI21, OAI22.

SPICE3f5 – simulate delay and leakage.

MAGIC – to implement layout of H/L variants

Leakage Comparison (HL / MTCMOS / Regular)

Leakage: HL,MTCMOS vs Regular  Leakage: HL vs MTCMOS At cell level, HL and MTCMOS leakage are comparably low

Circuit Leakage (Estimate vs SPICE)

 At circuit level, HL leakage is precisely estimable This is a key contribution  MTCMOS leakage is very unpredictable (due to floating nodes in standby )

Circuit Leakage (HL /MTCMOS)

 Design mapped for minimum area Design mapped for minimum delay Note the large circuit leakage range   for MTCMOS Circuit leakage (HL) is a single deterministic value Circuit leakage (HL) smaller than worst case MTCMOS circuit leakage.

Circuit Delay, Area Comparison

   Delay:  Performed “Exact Timing Analysis” to obtain largest sensitizable delay for circuit. Area:  Place / Route using CADENCE Silicon Ensemble.

  Used 4 routing layers.

MTCMOS: header and regular layout area. footer device areas added to Tested on 24 circuits from MCNC91 benchmark suite.

Delay comparison

   C ircuits mapped for minimum delay (SIS) Similar results if circuits mapped for minimum area (see paper) HL delay less than MTCMOS delay  O nly 1 transition slower in HL (both in MTCMOS )

Area Comparison (area mapped)

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Conclusions

Advantages:      Internal nodes of a gate never float.

 Leakage precisely estimable, unlike MTCMOS Delay increase only for one transition.

 We use only one supply gating device.

MTCMOS requires un-gated supply lines for memory elements.  We do not need separate supply lines  We use flip-flop design of Mutoh et. al. MTCMOS & HL leakage dramatically lower than regular designs  HL leakage lower than worst case MTCMOS leakage.

HL cell layout easily done  Header, footer regions free for over-the cell routing.

Disadvantages:  Determination of optimal primary input vector for minimal leakage is a complex problem.

 Can be solved using an ADD framework.

Thank you!