Transcript Lithography - Chemical Engineering IIT Madras

Intel 90 nm transistor
© Intel
90 nm node does NOT
necessarily mean that
gate (or M1 or any other
feature) is 90 nm
What does it mean?
Usually the “drawn”
size, in the layout,
before Optical
Proximity Correction
(OPC) or Mask Data
Preparation (MDP)
MOSFET: Manufacturing
Nitride
Oxidation
B
Poly
implant
Etch
Dep
etch
Poly
Etch
P
implant
Nitride
Gate Oxide
P Si
 Oxide strip
 Spacer formation
 Silicidation
MOSFET: Structure




Well deposition
LDD implant
RTA
Poly etch (cap oxide , for example)
 LOCOS
 DTI, STI
Silicide







Reacts only with Si and not with oxide / nitride
W, Ti, Co
Line width dependence
Concept of sheet resistance
Decrease in resistance
Using poly for high resistance (unsilicided)
SALICIDE
 Latch up
 LAYOUT for Transistor
Bipolar Transistor
Bit more realistic Schematic
Schematic
P
N
P
P
N
P
N